SPEC CPU2026 微观审视：程序、阶段与采样 ↗
英文原文 / English original 技术分析 摘要 本文从程序、阶段和采样三个层面，对SPEC CPU2026基准测试套件进行了详细的特性分析。作者
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SPEC CPU2026 Under the Microscope: Programs, Phases, and Samples ↗
AI Analysis Abstract This paper provides a detailed characterization of the SPEC CPU2026 benchmark suite across three levels: program, phase, and sample. The authors analyze whole-run metrics, compile
通过即时数据转换实现可编程数据布局 ↗
英文原文 / English original 技术分析 摘要 本文介绍了一个软硬件协同设计框架，包括数据转换语言 (DTL) 和数据转换单元 (DTU)，旨在解
Programmable Data Layouts via On-The-Fly Data Transformation ↗
AI Analysis Abstract This paper introduces a hardware-software co-design framework, comprising the Data Transformation Language (DTL) and the Data Transformation Unit (DTU), to address performance bot
我的RISC-V导师计划：那些无人指派给我的问题 ↗
英文原文 / English original 技术分析 摘要 前LFX RISC-V学员Rohit Sharma详细介绍了他在RISC-V ISA Explorer导师计划中的经历。除了完成指派的任务外
My RISC-V Mentorship: The Problems Nobody Assigned Me ↗
AI Analysis Abstract Rohit Sharma, a former LFX RISC-V mentee, details his experience in the RISC-V ISA Explorer mentorship program. Beyond his assigned milestones, he independently identified and add
Where the SRAM Goes: Reviewing the FreeRTOS-C and Embassy-Rust Memory Comparison ↗
AI Analysis Abstract A 13-page preprint compares FreeRTOS-C/lwIP with Embassy-Rust/smoltcp across eight firmware milestones on a 64 KiB RISC-V microcontroller. Its reported totals suggest substantial
V Questions with… DAMO Academy’s Dr. Jianyi Meng ↗
AI Analysis Abstract Alibaba DAMO Academy's XuanTie team achieved a significant AI milestone by running the Qwen3.8-27B large language model natively on a 64-core RISC-V C950 processor at over 30 toke
TALU: A Reconfigurable Tiled-ALU Grid for RISC-V ↗
AI Analysis Abstract TALU introduces a novel 5-stage RISC-V core featuring an N×N grid of registered ALU tiles in its execute stage, replacing a traditional single ALU. This reconfigurable, feed-forwa
Minimum RISC-V: Maximum FPGA Efficiency ↗
AI Analysis Abstract This paper introduces an optimization methodology for RISC-V soft processors on FPGAs, addressing the issue of large resource footprint and modest performance of general-purpose c
WeAct Logic Analyzer V2 – A $10 USB 3.0 logic analyzer board compatible with Sigrok/Pulseview (fork) ↗
AI Analysis Abstract The WeAct Logic Analyzer V2 is a compact, low-cost board based on the WCH CH32H417 dual-core RISC-V MCU, designed to function as a 16-channel USB 3.0 logic analyzer with up to 200
Agentic AI for Heterogeneous System Design Across Chip, Scale-Up, and Scale-Out Domains ↗
AI Analysis Abstract Modern AI and High-Performance Computing (HPC) systems face a rapidly expanding and complex design space, encompassing diverse compute architectures like GPUs, dataflow processors