The Future of Open Silicon

英文原文 / English original 技术分析 摘要 本文从程序、阶段和采样三个层面，对SPEC CPU2026基准测试套件进行了详细的特性分析。作者分析了x86、Arm和RISC-V架构上的全程运行指标、编译器和平台敏感性以及自顶向下瓶颈。研究揭示，全程平均值常常掩盖了基准测试执行中显著的时变行为，并将输入分为稳定型、多阶段型和突发型。关键的是，该研究根据硬件测量结果验证了广泛使用的SimPoint采样模拟方法，证明了其对于非稳定型输入的不准确性以及对随机种子的敏感性。研究结果表明，SimPoint的主要局限在于其代表性间隔的选择，而非其聚类机制，从而为更准确地对CPU2026进行采样模拟提供了实用建议。 核心要点 * 程序级分析显示，整数基准测试通常受前端限制，而浮点基准测试则常受内存限制，不同编译器版本可使单个基准测试的IPC减半或几乎翻倍。 * 阶段级特性分析揭示，超过一半的SPECrate输入表现出时变行为，单个输入运行中的IPC变化幅度超过一个数量级。 * SimPoint作为一种常见的采样模拟工具，

AI Analysis Abstract This paper provides a detailed characterization of the SPEC CPU2026 benchmark suite across three levels: program, phase, and sample. The authors analyze whole-run metrics, compiler and platform sensitivity, and top-down bottlenecks on x86, Arm, and RISC-V…

英文原文 / English original 技术分析 摘要 本文介绍了一个软硬件协同设计框架，包括数据转换语言 (DTL) 和数据转换单元 (DTU)，旨在解决由逻辑数据访问模式与物理内存布局不匹配引起的性能瓶颈。DTL 允许程序员表达复杂的数据布局重组，编译器将其转换为硬件配置。DTU 是一个位于末级缓存 (LLC) 和主内存之间的硬件引擎，它即时透明地评估这些配置，将分散的数据元素收集到密集、逻辑上连续的缓存行中。这种方法通过将布局转换转换为虚拟视图，消除了软件中显式数据具体化的需要。在 FireSim 中使用四核 RISC-V SoC 进行评估，DTU 在执行速度和内存效率方面取得了显著提升。 核心要点

AI Analysis Abstract This paper introduces a hardware-software co-design framework, comprising the Data Transformation Language (DTL) and the Data Transformation Unit (DTU), to address performance bottlenecks caused by misaligned logical data access patterns and physical memory…

英文原文 / English original 技术分析 摘要 前LFX RISC-V学员Rohit Sharma详细介绍了他在RISC-V ISA Explorer导师计划中的经历。除了完成指派的任务外，他还独立识别并解决了RISC-V生态系统中的关键挑战，从而开发并部署了两款重要工具：ISA Configuration Builder和Extension Sandbox。这些工具旨在通过利用RISC-V规范作为单一事实来源，简化RISC-V处理器配置和自定义指令的定义与验证过程，显著减少手动工作量和潜在错误。 核心要点 * 开发了ISA Configuration Builder，以简化RISC-V核心配置和依赖管理。 * 创建了Extension Sandbox，

AI Analysis Abstract Rohit Sharma, a former LFX RISC-V mentee, details his experience in the RISC-V ISA Explorer mentorship program. Beyond his assigned milestones, he independently identified and addressed critical challenges within the RISC-V ecosystem, leading to the…

AI Analysis Abstract A 13-page preprint compares FreeRTOS-C/lwIP with Embassy-Rust/smoltcp across eight firmware milestones on a 64 KiB RISC-V microcontroller. Its reported totals suggest substantial SRAM savings, but our PDF review found that the Embassy attribution categories…

AI Analysis Abstract Alibaba DAMO Academy's XuanTie team achieved a significant AI milestone by running the Qwen3.8-27B large language model natively on a 64-core RISC-V C950 processor at over 30 tokens per second, without requiring a discrete GPU or NPU. This accomplishment was…

AI Analysis Abstract TALU introduces a novel 5-stage RISC-V core featuring an N×N grid of registered ALU tiles in its execute stage, replacing a traditional single ALU. This reconfigurable, feed-forward spatial fabric is designed to overcome inefficiencies in lane-based RISC-V…

AI Analysis Abstract This paper introduces an optimization methodology for RISC-V soft processors on FPGAs, addressing the issue of large resource footprint and modest performance of general-purpose cores. The authors developed a lightweight, deeply pipelined RISC-V core capable…

AI Analysis Abstract The WeAct Logic Analyzer V2 is a compact, low-cost board based on the WCH CH32H417 dual-core RISC-V MCU, designed to function as a 16-channel USB 3.0 logic analyzer with up to 200 MHz bandwidth. It supports multiple applications, including logic analysis,…

AI Analysis Abstract Modern AI and High-Performance Computing (HPC) systems face a rapidly expanding and complex design space, encompassing diverse compute architectures like GPUs, dataflow processors, and RISC-V accelerators, various memory technologies, and multiple…