In-depth analysis, performance audits, and news for the RISC-V and Linux ecosystem.
英文原文 / English original 技术分析 摘要 前LFX RISC-V学员Rohit Sharma详细介绍了他在RISC-V ISA Explorer导师计划中的经历。除了完成指派的任务外，他还独立识别并解决了RISC-V生态系统中的关键挑战，从而开发并部署了两款重要工具：ISA Configuration Builder和Extension Sandbox。这些工具旨在通过利用RISC-V规范作为单一事实来源，简化RISC-V处理器配置和自定义指令的定义与验证过程，显著减少手动工作量和潜在错误。 核心要点 * 开发了ISA Configuration Builder，以简化RISC-V核心配置和依赖管理。 * 创建了Extension Sandbox，用于实时检测新RISC-V指令的冲突。 * 重写了ISA Explorer的同步引擎，自动化了1,867条指令在83个ISA子集中的路由。 * 重新设计了ISA
AI Analysis Abstract Rohit Sharma, a former LFX RISC-V mentee, details his experience in the RISC-V ISA Explorer mentorship program. Beyond his assigned milestones, he independently identified and addressed critical challenges within the RISC-V ecosystem, leading to the…
AI Analysis Abstract A 13-page preprint compares FreeRTOS-C/lwIP with Embassy-Rust/smoltcp across eight firmware milestones on a 64 KiB RISC-V microcontroller. Its reported totals suggest substantial SRAM savings, but our PDF review found that the Embassy attribution categories…
AI Analysis Abstract Alibaba DAMO Academy's XuanTie team achieved a significant AI milestone by running the Qwen3.8-27B large language model natively on a 64-core RISC-V C950 processor at over 30 tokens per second, without requiring a discrete GPU or NPU. This accomplishment was…
AI Analysis Abstract TALU introduces a novel 5-stage RISC-V core featuring an N×N grid of registered ALU tiles in its execute stage, replacing a traditional single ALU. This reconfigurable, feed-forward spatial fabric is designed to overcome inefficiencies in lane-based RISC-V…
AI Analysis Abstract This paper introduces an optimization methodology for RISC-V soft processors on FPGAs, addressing the issue of large resource footprint and modest performance of general-purpose cores. The authors developed a lightweight, deeply pipelined RISC-V core capable…
AI Analysis Abstract The WeAct Logic Analyzer V2 is a compact, low-cost board based on the WCH CH32H417 dual-core RISC-V MCU, designed to function as a 16-channel USB 3.0 logic analyzer with up to 200 MHz bandwidth. It supports multiple applications, including logic analysis,…
AI Analysis Abstract Modern AI and High-Performance Computing (HPC) systems face a rapidly expanding and complex design space, encompassing diverse compute architectures like GPUs, dataflow processors, and RISC-V accelerators, various memory technologies, and multiple…
AI Analysis Abstract Firmware diagnostic logging (printf) significantly burdens cycle-accurate RTL simulation, consuming 3.04 to 15.23 microseconds per call due to on-core formatting and memory-mapped I/O (MMIO) bus stalls. This paper introduces a host-side in-simulation…
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英文原文 / English original 技术分析 摘要 前LFX RISC-V学员Rohit Sharma详细介绍了他在RISC-V ISA Explorer导师计划中的经历。除了完成指派的任务外，他还独立识别并解决了RISC-V生态系统中的关键挑战，从而开发并部署了两款重要工具：ISA Configuration Builder和Extension Sandbox。这些工具旨在通过利用RISC-V规范作为单一事实来源，简化RISC-V处理器配置和自定义指令的定义与验证过程，显著减少手动工作量和潜在错误。 核心要点 * 开发了ISA Configuration
AI Analysis Abstract Rohit Sharma, a former LFX RISC-V mentee, details his experience in the RISC-V ISA Explorer mentorship program. Beyond his assigned milestones, he independently identified and addressed critical challenges within the RISC-V ecosystem, leading to the…
AI Analysis Abstract A 13-page preprint compares FreeRTOS-C/lwIP with Embassy-Rust/smoltcp across eight firmware milestones on a 64 KiB RISC-V microcontroller. Its reported totals suggest substantial SRAM savings, but our PDF review found that the Embassy attribution categories…
AI Analysis Abstract Alibaba DAMO Academy's XuanTie team achieved a significant AI milestone by running the Qwen3.8-27B large language model natively on a 64-core RISC-V C950 processor at over 30 tokens per second, without requiring a discrete GPU or NPU. This accomplishment was…
AI Analysis Abstract TALU introduces a novel 5-stage RISC-V core featuring an N×N grid of registered ALU tiles in its execute stage, replacing a traditional single ALU. This reconfigurable, feed-forward spatial fabric is designed to overcome inefficiencies in lane-based RISC-V…
AI Analysis Abstract This paper introduces an optimization methodology for RISC-V soft processors on FPGAs, addressing the issue of large resource footprint and modest performance of general-purpose cores. The authors developed a lightweight, deeply pipelined RISC-V core capable…
AI Analysis Abstract The WeAct Logic Analyzer V2 is a compact, low-cost board based on the WCH CH32H417 dual-core RISC-V MCU, designed to function as a 16-channel USB 3.0 logic analyzer with up to 200 MHz bandwidth. It supports multiple applications, including logic analysis,…
AI Analysis Abstract Modern AI and High-Performance Computing (HPC) systems face a rapidly expanding and complex design space, encompassing diverse compute architectures like GPUs, dataflow processors, and RISC-V accelerators, various memory technologies, and multiple…
AI Analysis Abstract Firmware diagnostic logging (printf) significantly burdens cycle-accurate RTL simulation, consuming 3.04 to 15.23 microseconds per call due to on-core formatting and memory-mapped I/O (MMIO) bus stalls. This paper introduces a host-side in-simulation…
AI Analysis Abstract SoCMake, a component of the System-on-Chip Radiation-Tolerant Ecosystem (SOCRATES), is being developed to produce modular RISC-V SoCs for radiation-harsh and safety-critical environments. This work explores the early adoption of programmable SoCs in ASIC…
AI Analysis Abstract This paper addresses the suboptimal performance of FlashAttention on long-vector RISC-V processors, specifically the EPAC chip, where the PyTorch CPU kernel achieves only 16.2% of peak floating-point utilization. The inefficiencies stem from misaligned…
AI Analysis Abstract The LILYGO T-Display K230 is a handheld development kit built around the Canaan Kendryte K230 dual-core 64-bit RISC-V processor, which includes an integrated AI accelerator. It features a 4.1-inch AMOLED touchscreen, 1GB LPDDR4 RAM, a 2MP camera, and…
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