In-depth analysis, performance audits, and news for the RISC-V and Linux ecosystem.
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Member contentAI Analysis Abstract The LILYGO T-Display K230 is a handheld development kit built around the Canaan Kendryte K230 dual-core 64-bit RISC-V processor, which includes an integrated AI accelerator. It features a 4.1-inch AMOLED touchscreen, 1GB LPDDR4 RAM, a 2MP camera, and…
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Member contentAI Analysis Abstract Two independent open-source projects, Ziro Designer/ZiroEDA and KiCad Android, now enable KiCad 10 to run unofficially in a web browser or as a native Android application. These developments expand KiCad's accessibility to platforms like RISC-V, Android…
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Member contentAI Analysis Abstract LabWired is an MIT-licensed MCU firmware simulation core designed to accelerate firmware testing. It executes compiled firmware against simulated CPUs and peripherals, capturing output and register states, and supports repeatable checks in Continuous…
RISC-V
Member contentAI Analysis Abstract This work demonstrates real-time, open-vocabulary streaming speech recognition on a microcontroller using Kroko, a 65.7M-parameter Zipformer2 transducer. The system runs on an ESP32-P4, which features dual 400 MHz RISC-V cores and a 128-bit SIMD extension…
RISC-V
Member contentAI Analysis Abstract This work introduces a development environment that integrates LLM agents with FPGA-in-the-loop evaluation for designing RISC-V CPUs. The system allows LLM agents to implement CPU candidates on an FPGA and utilize on-board performance measurements to guide…
RISC-V
Member contentAI Analysis Abstract RV2GC is a system designed for programmable garbled-circuit execution in a RISC-V processor, addressing the inefficiencies of traditional complete garbled processors that repeatedly traverse large, fixed circuits. It reconstructs the garbling boundary by…
RISC-V
Member contentAI Analysis Abstract This paper presents the first comprehensive hardware study of four state-of-the-art randomized cache designs—Ceaser-S, ScatterCache, SassCache, and Mirage—integrated into the last-level cache of a multi-core out-of-order RISC-V System-on-Chip. The research…
RISC-V
Member contentAI Analysis Abstract This letter details a mixed-precision CNN-LSTM accelerator designed for EEG-based sleep staging. It incorporates a serpentine dataflow to efficiently process long temporal convolutions, significantly reducing memory accesses compared to conventional methods.…
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Member contentAI Analysis Abstract The Banana Pi BPI-M8 is a credit card-sized single board computer featuring an Allwinner A733 octa-core SoC, 4GB LPDDR5, and various connectivity options. It includes a RISC-V E902 real-time core, a 3 TOPS NPU, a PCIe FFC connector, and a UFS module socket.…
RISC-V
Member contentAI Analysis Abstract Wolfpine is an open-source RISC-V simulator developed for Tenstorrent's Tensix architecture, supporting both Wormhole and Blackhole generations. It integrates seamlessly with the TT-Metal software stack and was constructed entirely from publicly available…
RISC-V
Member contentAI Analysis Abstract Atik is an open-source RoCC accelerator for RocketChip, designed to accelerate transformer inference by executing dense matrix multiplication and attention operations. It utilizes a shared fixed-point MAC mesh and processes BF16 tensors. A streaming…
Research
Member contentAbstract The Proceedings of the 15th ACM SIGPLAN CPP '26 compile cutting-edge research focused on the intersection of formal verification and practical program development. This conference showcases innovations in using proof assistants, type theory, and logic to mathematically…
Research
Member contentAbstract The Proceedings of the 12th International Conference on Next Generation Computing, Communication, Systems and Security (NSysS '25) compiles cutting-edge research focused on the convergence of advanced digital technologies. This volume addresses critical challenges in…
Research
Member contentAbstract The Proceedings of the 37th Australian Conference on Human-Computer Interaction (OzCHI '25) collects pivotal research focused on advancing user experience, interface design, and interaction methodologies for emerging technologies. Key themes include the intersection of…
Linux
Member contentAbstract New Linux patches are enabling Intel discrete GPU firmware updates on non-x86 architectures, such as ARM and RISC-V. Previously, this functionality was restricted because the Intel Management Engine Interface (MEI) driver was too closely tied to x86 architecture. These…
News
Member contentAbstract The article provides a review of the MUSE Book, an octa-core RISC-V laptop running Linux, focusing on its performance and viability in the projected 2026 computing landscape. This testing marks a significant step forward, demonstrating the successful integration of a…
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Member contentAbstract The MUSE Book RISC-V laptop, featuring the SpacemiT K1/M1 octa-core SoC, demonstrates the maturation of the RISC-V hardware ecosystem into a consumer form factor. The 2026 review specifically prioritizes evaluating software progress, centering on the performance and…
Research
Member contentAbstract This work introduces a novel approach for synthesizing practical Abstract Transformers tailored for the MLIR compiler infrastructure. By automating the generation of these crucial components, the system significantly reduces the manual engineering effort required to…
Research
Member contentAbstract ChiSA introduces a novel static analysis framework specifically designed for lightweight verification of hardware designs written in the Chisel HDL. This approach allows developers to detect common design errors, structural inconsistencies, and unsafe operations early…
Research
Member contentAbstract ArchSem introduces a novel, reusable framework for defining the rigorous semantics of complex relaxed computer architectures. This approach allows developers and verification engineers to formally specify weak memory models (WMMs) in a modular way, addressing the…
Research
Member contentAbstract This article introduces a novel methodology for the foundational verification of running-time bounds, specifically addressing the complexities of interactive programs. It establishes a formal framework capable of mathematically certifying Worst-Case Execution Time…
News
Member contentAbstract The Digitimes article assesses the rapid expansion of the RISC-V Instruction Set Architecture (ISA) in the global semiconductor market. It hypothesizes that, based on current industry trends and accelerated adoption, RISC-V is positioned to solidify its role as the…
News
Member contentAbstract SiFive has introduced its 2nd Generation Intelligence Cores, significantly accelerating the RISC-V movement into the high-performance computing and AI processing markets. These advanced cores are specifically designed to handle intense machine learning workloads,…
News
Member contentAbstract Major technology leaders Meta and Qualcomm are aggressively integrating RISC-V into their semiconductor strategies, validating the open-source instruction set architecture (ISA). This strategic push is projected to propel RISC-V's market share towards a significant 25%…
RISC-V
Member contentAbstract The RISC-V instruction set architecture (ISA) has achieved a significant milestone, claiming roughly 25% of the global processor market share. This rapid adoption is driven by its open, modular architecture, enabling broad use across diverse applications including…
News
Member contentAbstract The RISC-V open-source architecture has achieved a significant milestone, reaching 25% market penetration in relevant sectors. This substantial growth is primarily driven by massive adoption and investment from major industry players, specifically Meta and Qualcomm.…
News
Member contentAbstract Andrew “bunnie” Huang has designed a new RISC-V development board characterized by its commitment to a “mostly open” hardware philosophy. This project leverages the royalty-free RISC-V architecture to create a transparent, developer-friendly platform. The initiative…
News
Member contentAbstract Qualcomm’s acquisition of Ventana Micro Systems marks a pivotal moment, validating the RISC-V architecture's readiness to compete in high-performance computing markets traditionally dominated by ARM and x86. Ventana specializes in large-core RISC-V designs, which…
News
Member contentAbstract This opinion piece highlights the escalating geopolitical rivalry between the United States (NASA) and China for supremacy in space exploration, warning that China is aggressively pursuing space dominance. The article argues that the U.S. must significantly bolster its…
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Member contentAbstract Nordic Semiconductor has introduced the nRF54LM20B wireless SoC, the first nRF54L microcontroller to integrate a dedicated 128 MHz Axon Neural Processing Unit (NPU) for high-efficiency edge AI tasks. This NPU delivers substantial performance benefits, claiming up to 7…
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Member contentAbstract Espressif Systems showcased two new RISC-V microcontrollers at CES 2026: the high-performance ESP32-E22 Wi-Fi 6E SoC and the ultra-low-power ESP32-H21 Bluetooth LE MCU. The ESP32-E22 features a dual-core 500 MHz RISC-V CPU and tri-band Wi-Fi 6E capable of up to 2.1 Gbps…
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Member contentAbstract The Openterface KVM-GO is an ultra-compact, open-source KVM-over-USB solution designed for troubleshooting headless devices and remote server monitoring. This keychain-sized gadget, powered by a WCH CH32V208 RISC-V MCU, features interchangeable models supporting direct…
News
Member contentAbstract Allwinner has introduced the V861, a new dual-core 64-bit RISC-V System-in-Package (SiP) specifically designed for advanced AI camera applications. This chip integrates 128MB of DDR3L memory directly, significantly simplifying hardware design and reducing…
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Member contentAbstract The Allwinner V861 is a new dual-core 64-bit RISC-V SiP optimized for 4K AI camera applications, notably integrating 128MB DDR3L and a 1 TOPS NPU. It utilizes XuanTie C907 and E907 cores, offering H.265 encoding up to 4Kp25 for high-resolution video processing.…
News
Member contentAbstract WCH has announced the CH32H417, a new dual-core RISC-V MCU designed for high-speed data handling in embedded systems. The key innovation is the integration of advanced connectivity features, including native USB 3.0 support and a proprietary 500MB/s Ultra-High Speed…
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Member contentAbstract The WCH CH32H417 is a newly released dual-core RISC-V microcontroller featuring primary cores clocked up to 400 MHz and substantial integrated memory (960 KB Flash/896 KB SRAM). Its key innovation is the inclusion of high-bandwidth connectivity options rarely found in…
Research
Member contentAbstract I-COR is a novel instruction-level fault tolerance mechanism specifically designed to protect the Register File (RF) in simple 3-stage pipeline RISC-V processors. This approach leverages instruction context to selectively introduce redundancy, thereby effectively…
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Member contentAbstract This 2026 review of the low-cost StarFive VisionFive 2 Lite SBC, based on the JH7110S RISC-V SoC, demonstrates significant maturation in the platform’s core Linux support by successfully booting Ubuntu 24.04. The board provides an accessible entry point to RISC-V…
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Member contentAbstract The DFRobot HUSKYLENS 2 is a next-generation AI vision sensor leveraging a Kendryte K230 dual-core RISC-V SoC paired with a potent 6 TOPS AI accelerator, ensuring fast, low-latency, on-device machine vision processing. The device features a 2.4-inch IPS touchscreen,…
News
Member contentAbstract The Bit-Brick Cluster K1 introduces a new solution for creating powerful, multi-core RISC-V computers through modular assembly. This system achieves a 32-core configuration by physically clustering four individual SpacemiT K1 single-board computers (SBCs). This…
News
Member contentAbstract Lingshuo Technology successfully secured Angel funding to accelerate its mission of developing specialized automotive-grade chips utilizing the RISC-V architecture. This investment underscores growing confidence in the RISC-V ecosystem's ability to meet the stringent…
News
Member contentAbstract Ethereum co-founder Vitalik Buterin announced that the platform is pivoting away from the previously planned eWASM (Ethereum WebAssembly) execution environment. The project is instead focusing on adopting the open-source RISC-V Instruction Set Architecture (ISA) for its…
News
Member contentAbstract The technical article reports on a significant architectural pivot within the Ethereum ecosystem, announcing the abandonment of the previously planned eWASM (Ethereum WebAssembly) virtual machine standard. Ethereum is instead shifting its focus towards adopting and…
News
Member contentAbstract The Bit-Brick Cluster K1 is a new 4-slot RISC-V cluster board designed to utilize the SpacemiT K1-based SSOM-K1 system-on-module, enabling compact, multi-node computing. This platform facilitates the development and testing of parallel processing and distributed…
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Member contentAbstract The Bit-Brick Cluster K1 is a specialized cluster board designed to house up to four SSOM-K1 system-on-modules, powered by the SpacemiT K1 octa-core RISC-V processor optimized for high-performance edge computing. The board facilitates robust scaling via an integrated…
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Member contentAbstract Waveshare introduces the ESP32-C6-Touch-AMOLED-1.8, a compact development board leveraging the ESP32-C6 SoC, which features a single-core 32-bit RISC-V CPU and comprehensive wireless connectivity including Wi-Fi 6, Bluetooth 5 LE, Zigbee, and Thread. The board…
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Member contentAbstract The M5Stack NanoH2 is an ultra-compact, standalone IoT development kit built around the Espressif ESP32-H2 system-on-chip, specifically optimized for smart home applications. It provides critical multi-protocol wireless connectivity, natively supporting Zigbee, Thread,…
News
Member contentAbstract RISC-V has reached a critical adoption milestone, achieving 25% market penetration across the silicon industry. This significant growth is spearheaded by major technology firms, specifically citing Qualcomm and Meta, who are championing the transition to open-source…
News
Member contentAbstract The German chip development tools company, TASKING, has joined the open RISC-V automotive alliance, signaling increased industry commitment to the open-standard architecture within the vehicle technology sector. This membership enhances the alliance's ability to provide…
News
Member contentAbstract Tenstorrent, led by legendary chip architect Jim Keller, has announced the launch of Ascalon, a new high-performance RISC-V processor intellectual property (IP) core. This powerful new design is explicitly aimed at disrupting the lucrative data center market, posing a…
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