In-depth analysis, performance audits, and news for the RISC-V and Linux ecosystem.
Research
Abstract The Proceedings of the 15th ACM SIGPLAN CPP '26 compile cutting-edge research focused on the intersection of formal verification and practical program development. This conference showcases innovations in using proof assistants, type theory, and logic to mathematically guarantee the correctness and security of programs and systems. It
Research
Abstract The Proceedings of the 12th International Conference on Next Generation Computing, Communication, Systems and Security (NSysS '25) compiles cutting-edge research focused on the convergence of advanced digital technologies. This volume addresses critical challenges in developing resilient systems, secure architectures, and high-performance network solutions for the future.
Research
Abstract The Proceedings of the 37th Australian Conference on Human-Computer Interaction (OzCHI '25) collects pivotal research focused on advancing user experience, interface design, and interaction methodologies for emerging technologies. Key themes include the intersection of artificial intelligence and human interaction, designing accessible systems, and exploring immersive environments like
Linux
Abstract New Linux patches are enabling Intel discrete GPU firmware updates on non-x86 architectures, such as ARM and RISC-V. Previously, this functionality was restricted because the Intel Management Engine Interface (MEI) driver was too closely tied to x86 architecture. These changes decouple the MEI from the GPU drivers,
News
Abstract The article provides a review of the MUSE Book, an octa-core RISC-V laptop running Linux, focusing on its performance and viability in the projected 2026 computing landscape. This testing marks a significant step forward, demonstrating the successful integration of a high-core-count RISC-V chip into
Embedded
Abstract The MUSE Book RISC-V laptop, featuring the SpacemiT K1/M1 octa-core SoC, demonstrates the maturation of the RISC-V hardware ecosystem into a consumer form factor. The 2026 review specifically prioritizes evaluating software progress, centering on the performance and usability of Bianbu OS 2.3 (Ubuntu 24.
Research
Abstract This work introduces a novel approach for synthesizing practical Abstract Transformers tailored for the MLIR compiler infrastructure. By automating the generation of these crucial components, the system significantly reduces the manual engineering effort required to implement sound static analyses like data flow and shape inference. This methodology enhances the
Research
Abstract ChiSA introduces a novel static analysis framework specifically designed for lightweight verification of hardware designs written in the Chisel HDL. This approach allows developers to detect common design errors, structural inconsistencies, and unsafe operations early in the development lifecycle without requiring resource-intensive simulation or heavy formal verification. By
Research
Abstract ArchSem introduces a novel, reusable framework for defining the rigorous semantics of complex relaxed computer architectures. This approach allows developers and verification engineers to formally specify weak memory models (WMMs) in a modular way, addressing the ambiguity inherent in natural language specifications. By providing a sound, compositional foundation, ArchSem
Research
Abstract This article introduces a novel methodology for the foundational verification of running-time bounds, specifically addressing the complexities of interactive programs. It establishes a formal framework capable of mathematically certifying Worst-Case Execution Time (WCET) guarantees directly from the program's low-level semantics. This innovation ensures rigorous,
News
Abstract The Digitimes article assesses the rapid expansion of the RISC-V Instruction Set Architecture (ISA) in the global semiconductor market. It hypothesizes that, based on current industry trends and accelerated adoption, RISC-V is positioned to solidify its role as the world's third major CPU ecosystem. This
News
Abstract SiFive has introduced its 2nd Generation Intelligence Cores, significantly accelerating the RISC-V movement into the high-performance computing and AI processing markets. These advanced cores are specifically designed to handle intense machine learning workloads, leveraging RISC-V's customizable Instruction Set Architecture for superior efficiency and specialized
News
Abstract Major technology leaders Meta and Qualcomm are aggressively integrating RISC-V into their semiconductor strategies, validating the open-source instruction set architecture (ISA). This strategic push is projected to propel RISC-V's market share towards a significant 25% milestone across specific high-growth segments. Their collaboration signals
RISC-V
Abstract The RISC-V instruction set architecture (ISA) has achieved a significant milestone, claiming roughly 25% of the global processor market share. This rapid adoption is driven by its open, modular architecture, enabling broad use across diverse applications including automotive, data center, and embedded systems. This growth underscores a major
News
Abstract The RISC-V open-source architecture has achieved a significant milestone, reaching 25% market penetration in relevant sectors. This substantial growth is primarily driven by massive adoption and investment from major industry players, specifically Meta and Qualcomm. This validates RISC-V's viability as a mainstream, royalty-free
News
Abstract Andrew “bunnie” Huang has designed a new RISC-V development board characterized by its commitment to a “mostly open” hardware philosophy. This project leverages the royalty-free RISC-V architecture to create a transparent, developer-friendly platform. The initiative significantly boosts the credibility and available resources within the open-
News
Abstract Qualcomm’s acquisition of Ventana Micro Systems marks a pivotal moment, validating the RISC-V architecture's readiness to compete in high-performance computing markets traditionally dominated by ARM and x86. Ventana specializes in large-core RISC-V designs, which Qualcomm will leverage to rapidly deploy open-standard
News
Abstract This opinion piece highlights the escalating geopolitical rivalry between the United States (NASA) and China for supremacy in space exploration, warning that China is aggressively pursuing space dominance. The article argues that the U.S. must significantly bolster its commitment and funding to NASA to safeguard its future and
Embedded
Abstract Nordic Semiconductor has introduced the nRF54LM20B wireless SoC, the first nRF54L microcontroller to integrate a dedicated 128 MHz Axon Neural Processing Unit (NPU) for high-efficiency edge AI tasks. This NPU delivers substantial performance benefits, claiming up to 7 times faster speeds and 8 times higher energy efficiency compared
Embedded
Abstract Espressif Systems showcased two new RISC-V microcontrollers at CES 2026: the high-performance ESP32-E22 Wi-Fi 6E SoC and the ultra-low-power ESP32-H21 Bluetooth LE MCU. The ESP32-E22 features a dual-core 500 MHz RISC-V CPU and tri-band Wi-Fi 6E capable
Embedded
Abstract The Openterface KVM-GO is an ultra-compact, open-source KVM-over-USB solution designed for troubleshooting headless devices and remote server monitoring. This keychain-sized gadget, powered by a WCH CH32V208 RISC-V MCU, features interchangeable models supporting direct HDMI, DisplayPort, or VGA input up to 4K @ 60
News
Abstract Allwinner has introduced the V861, a new dual-core 64-bit RISC-V System-in-Package (SiP) specifically designed for advanced AI camera applications. This chip integrates 128MB of DDR3L memory directly, significantly simplifying hardware design and reducing bill-of-materials costs for manufacturers. The V861 is capable of
Embedded
Abstract The Allwinner V861 is a new dual-core 64-bit RISC-V SiP optimized for 4K AI camera applications, notably integrating 128MB DDR3L and a 1 TOPS NPU. It utilizes XuanTie C907 and E907 cores, offering H.265 encoding up to 4Kp25 for high-resolution video processing. Supported by
News
Abstract WCH has announced the CH32H417, a new dual-core RISC-V MCU designed for high-speed data handling in embedded systems. The key innovation is the integration of advanced connectivity features, including native USB 3.0 support and a proprietary 500MB/s Ultra-High Speed Interface (UHSIF). This powerful
Embedded
Abstract The WCH CH32H417 is a newly released dual-core RISC-V microcontroller featuring primary cores clocked up to 400 MHz and substantial integrated memory (960 KB Flash/896 KB SRAM). Its key innovation is the inclusion of high-bandwidth connectivity options rarely found in MCUs, specifically a 5 Gbps
Research
Abstract I-COR is a novel instruction-level fault tolerance mechanism specifically designed to protect the Register File (RF) in simple 3-stage pipeline RISC-V processors. This approach leverages instruction context to selectively introduce redundancy, thereby effectively mitigating soft errors affecting stored register data. The resulting innovation provides high
Embedded
Abstract This 2026 review of the low-cost StarFive VisionFive 2 Lite SBC, based on the JH7110S RISC-V SoC, demonstrates significant maturation in the platform’s core Linux support by successfully booting Ubuntu 24.04. The board provides an accessible entry point to RISC-V development with modern connectivity
Embedded
Abstract The DFRobot HUSKYLENS 2 is a next-generation AI vision sensor leveraging a Kendryte K230 dual-core RISC-V SoC paired with a potent 6 TOPS AI accelerator, ensuring fast, low-latency, on-device machine vision processing. The device features a 2.4-inch IPS touchscreen, offers over 15
News
Abstract The Bit-Brick Cluster K1 introduces a new solution for creating powerful, multi-core RISC-V computers through modular assembly. This system achieves a 32-core configuration by physically clustering four individual SpacemiT K1 single-board computers (SBCs). This development provides an accessible and scalable method for enthusiasts and
News
Abstract Lingshuo Technology successfully secured Angel funding to accelerate its mission of developing specialized automotive-grade chips utilizing the RISC-V architecture. This investment underscores growing confidence in the RISC-V ecosystem's ability to meet the stringent demands of the safety-critical automotive industry. The company is positioning
News
Abstract Ethereum co-founder Vitalik Buterin announced that the platform is pivoting away from the previously planned eWASM (Ethereum WebAssembly) execution environment. The project is instead focusing on adopting the open-source RISC-V Instruction Set Architecture (ISA) for its future execution needs. This major architectural shift was necessitated by
News
Abstract The technical article reports on a significant architectural pivot within the Ethereum ecosystem, announcing the abandonment of the previously planned eWASM (Ethereum WebAssembly) virtual machine standard. Ethereum is instead shifting its focus towards adopting and integrating the open-source RISC-V Instruction Set Architecture (ISA) for its next-generation
News
Abstract The Bit-Brick Cluster K1 is a new 4-slot RISC-V cluster board designed to utilize the SpacemiT K1-based SSOM-K1 system-on-module, enabling compact, multi-node computing. This platform facilitates the development and testing of parallel processing and distributed computing applications built upon the RISC-
Embedded
Abstract The Bit-Brick Cluster K1 is a specialized cluster board designed to house up to four SSOM-K1 system-on-modules, powered by the SpacemiT K1 octa-core RISC-V processor optimized for high-performance edge computing. The board facilitates robust scaling via an integrated Gigabit Ethernet switch chip,
Embedded
Abstract Waveshare introduces the ESP32-C6-Touch-AMOLED-1.8, a compact development board leveraging the ESP32-C6 SoC, which features a single-core 32-bit RISC-V CPU and comprehensive wireless connectivity including Wi-Fi 6, Bluetooth 5 LE, Zigbee, and Thread. The board integrates a high-quality 1.
Embedded
Abstract The M5Stack NanoH2 is an ultra-compact, standalone IoT development kit built around the Espressif ESP32-H2 system-on-chip, specifically optimized for smart home applications. It provides critical multi-protocol wireless connectivity, natively supporting Zigbee, Thread, and the Matter standard. Unlike earlier models, this device functions as a
News
Abstract RISC-V has reached a critical adoption milestone, achieving 25% market penetration across the silicon industry. This significant growth is spearheaded by major technology firms, specifically citing Qualcomm and Meta, who are championing the transition to open-source silicon architectures. Their collective leadership demonstrates a profound shift in the
News
Abstract The German chip development tools company, TASKING, has joined the open RISC-V automotive alliance, signaling increased industry commitment to the open-standard architecture within the vehicle technology sector. This membership enhances the alliance's ability to provide robust, commercial-grade development tools necessary for high-integrity and
News
Abstract Tenstorrent, led by legendary chip architect Jim Keller, has announced the launch of Ascalon, a new high-performance RISC-V processor intellectual property (IP) core. This powerful new design is explicitly aimed at disrupting the lucrative data center market, posing a direct threat to the dominance of established ARM
News
Abstract The article compilation titled 'Top 10 articles of 2025' from embedded.com likely serves as a critical retrospective, reviewing the year's most significant technological advancements and paradigm shifts within the embedded industry. These top trends would undoubtedly highlight the accelerating commercialization of RISC-V, particularly
News
Abstract The RISC-V ISA is emerging as the premier open-source alternative, directly challenging ARM's historical dominance in the chip industry. Its key advantages include flexibility, royalty-free licensing, and architectural adaptability for diverse applications, spanning embedded systems to high-performance computing. This rise signifies a major
News
Abstract A new strategic partnership has been formed specifically to accelerate the integration and validation of the RISC-V instruction set architecture within the automotive industry. This collaboration addresses the stringent requirements of modern vehicle systems, including functional safety (ISO 26262 compliance), real-time performance, and robust security. The initiative
Linux
Abstract Qualcomm's proprietary Xqci RISC-V vendor extension has officially transitioned from experimental status to stable within the LLVM compiler toolchain. This critical change was recently committed to the LLVM Git repository in preparation for the LLVM 22 release. The designation shift signifies the maturity and production readiness
Research
Abstract This survey paper meticulously tracks the technological progression from traditional Tiny Machine Learning (TinyML) to the sophisticated deployment of Tiny Deep Learning (TinyDL) on highly resource-constrained edge devices. It systematically reviews cutting-edge advancements in model compression, efficient neural network architectures, and optimizing the hardware/software interface necessary
News
Abstract Parrot OS 7.0, the specialized ethical hacking and security distribution, has been officially released with significant updates. This version introduces support for the KDE Plasma desktop environment, offering users more customization choices. Crucially, Parrot 7.0 now provides native support for the RISC-V architecture, expanding the accessibility
News
Abstract Qualcomm's specialized Xqci extension for RISC-V architecture has been officially designated as non-experimental within the upcoming LLVM 22 compiler infrastructure release. This transition signifies the maturity and stability of the extension, confirming its readiness for broader commercial and production deployment. The integration ensures that developers
Research
Abstract This paper investigates the security of the CVA6 RISC-V core against power side-channel attacks by employing an RTL-level power profiling framework called VeriSide. The analysis targeted a software-based AES encryption implementation and utilized Correlation Power Analysis (CPA). The research successfully demonstrated significant power leakage, enabling
News
Abstract RISC-V is fundamentally shifting the semiconductor landscape, becoming a global hedge against pervasive geopolitical volatility and restrictive licensing wars. This 'Great Architecture Pivot' is driven by the necessity for open, resilient, and sovereign technology solutions in the face of increasing trade tensions. The open-source instruction
Research
Abstract This work introduces a novel 'On-Demand' architecture for regular expression matching implemented on FPGAs, specifically designed to maximize efficiency in Deep Packet Inspection (DPI) environments. The key innovation involves dynamically configuring and activating hardware finite automata resources only when traffic patterns necessitate specific rule matching, drastically
News
Abstract GigaDevice has unveiled the GD32VW553-UNIFI, a highly cost-effective wireless IoT module leveraging the RISC-V architecture and priced aggressively around $2. This module integrates cutting-edge connectivity, featuring both WiFi 6 (802.11ax) and Bluetooth 5.2 Low Energy capabilities. The combination of advanced standards and low
Embedded
Abstract The GigaDevice GD32VW553-UNIFI is a new, highly competitive wireless IoT module based on an integrated GD32VW553 RISC-V microcontroller, available at an ultra-low price point of approximately $2+. This module uniquely offers both 2.4 GHz WiFi 6 (802.11ax) and Bluetooth 5.2 LE connectivity, bringing
Research
Abstract This article, the second in a historical series, critiques the persistent limitations and error propagation issues inherent in traditional IEEE 754 floating-point standards. It introduces a 'revolutionary new approach' to real number computation designed to significantly enhance numerical precision and rigor, particularly in high-demand scientific
News
Abstract Qualcomm's acquisition of RISC-V chip designer Ventana Micro marks a significant shift in the competitive landscape of processor IP. This strategic move immediately caused a sharp decline in Arm's stock value, indicating market concern over rising RISC-V adoption backed by major industry players.
Embedded
Abstract Seeed Studio launched the XIAO Soil Moisture Sensor, an ultra-low power device powered by the XIAO ESP32C6 module utilizing dual RISC-V cores for extended battery life on a single AA battery. Preloaded with ESPHome, the sensor is designed for indoor plant monitoring and offers immediate, seamless integration
News
Abstract The How-To Geek article presents a curated list of five indispensable open-source projects that the author advocates for financially supporting. This editorial piece highlights the importance of user donations for maintaining and advancing critical FOSS infrastructure and applications. The core message is a call for greater user
Research
Abstract PermuteV is a performant side-channel resistant RISC-V core designed to secure Edge AI inference models against physical attacks, which frequently expose confidential neural network data. The core employs a novel hardware-accelerated defense mechanism that randomly permutes the execution order of loop iterations to obfuscate sensitive electromagnetic
Embedded
Abstract Elecrow has launched the "All-in-One Starter Kit for ESP32-P4," an open-source learning and prototyping platform built around the dual-core RISC-V ESP32-P4 chip. This comprehensive kit features a 7-inch touchscreen, a 2MP camera, and sixteen integrated modules, streamlining development for
Embedded
Abstract Waveshare has introduced the RP2350-Touch-LCD-1.85C devkit, built around the new Raspberry Pi RP2350A microcontroller, which features a 1.85-inch round touchscreen and integrated audio capabilities for HMI solutions. The core innovation lies in the RP2350 MCU’s hybrid architecture, offering developers the choice of
News
Abstract eeNews Europe has issued a specialized Call for Presentations (CfP) centered on advancing the implementation and ecosystem of the open-standard RISC-V architecture. The invitation targets proposals showcasing cutting-edge developments in three high-priority sectors: Embedded systems, Artificial Intelligence (AI), and Automotive technology. This focus highlights the
RISC-V
Abstract RISC-V International announced the recipients of the 2025 AI & RISC-V Gemini Credit grants, a program designed to leverage AI models to significantly accelerate the RISC-V software ecosystem. Recipients receive up to $50,000 USD in Gemini compute credits to pursue projects focusing on AI-driven
News
Abstract Intel has released version 1.29 of its Implicit SPMD Program Compiler (ISPC), marking a significant update that focuses on modernization and architecture expansion. The release notably discontinues support for older Gen9 integrated GPU targets to streamline the codebase and introduces several new performance optimizations. Crucially, ISPC 1.29
Research
Abstract This article details the historical trajectory and evolution of formal methods (FM) research and practical application within the technological landscape of China. It chronicles key academic milestones, influential research institutions, and major industrial achievements, establishing a comprehensive historical context for domestic verification capabilities. The analysis provides crucial insight into
News
Abstract The analysis forecasts a significant open-source chip shift driven by AI acceleration, positioning the customizable RISC-V architecture as a powerful challenger to established proprietary instruction sets like Arm and x86. By 2025, RISC-V’s modularity and extensibility are expected to fuel its rapid adoption in specialized
News
Abstract Newer, high-performance RISC-V CPUs have been confirmed vulnerable to the classic Spectre Variant 1 (V1) speculative execution side-channel attack. This discovery highlights that RISC-V implementations adopting modern performance features, such as deep pipelines, inherit established microarchitectural security flaws. Immediate action has been taken by the
Research
Abstract ChatArch introduces a novel Knowledge-driven Graph-of-thought (GoT) LLM framework designed to automate and optimize the challenging process of processor architecture design. By integrating domain-specific knowledge graphs, ChatArch facilitates structured, multi-path reasoning for evaluating complex architectural trade-offs, surpassing the limitations of sequential LLM chains.
News
Abstract A newly introduced co-emulation platform is specifically engineered to handle the high complexity and customizability inherent in advanced RISC-V chip designs. This verification solution integrates high-speed hardware emulation with software simulation, enabling designers to efficiently test customized instruction set extensions and multi-core architectures. The platform
News
Abstract A newly introduced co-emulation platform is specifically engineered to handle the high complexity and customizability inherent in advanced RISC-V chip designs. This verification solution integrates high-speed hardware emulation with software simulation, enabling designers to efficiently test customized instruction set extensions and multi-core architectures. The platform
News
Originally published on Google News - RISC-V Tenstorrent advances RISC-V AI chips in China with former Arm China CEO DIGITIMES Asia
News
Abstract SiFive and IAR Systems have announced a collaboration aimed at significantly enhancing the RISC-V automotive toolchain. This partnership integrates IAR's certified Embedded Workbench with SiFive's automotive processor IP, providing robust and safety-compliant development solutions. The initiative is critical for accelerating the adoption of
News
Abstract Tenstorrent is strategically advancing its RISC-V AI chip initiative within the crucial Chinese market. This expansion is bolstered by the involvement of the former CEO of Arm China, signaling a high-profile move to gain traction against incumbent architectures. The collaboration aims to accelerate the deployment and adoption
News
Abstract India has unveiled the DHRUV64, an indigenously developed dual-core processor utilizing the open-source RISC-V architecture. This chip operates at a clock speed of 1GHz, signaling a major step toward India’s goal of achieving technological self-reliance in silicon design. The introduction of the DHRUV64 contributes
News
Abstract The Reuters Breakingviews article predicts that open-standard chips, most notably those based on architectures like RISC-V, will emerge as the unexpected 'dark horse' in the AI hardware market by 2026. This forecasted disruption is driven by the industry's necessity for highly customized and
Research
Abstract This paper presents a novel, quantum-resistant (QR) firmware update architecture designed to secure the critical Firmware Over-The-Air (FOTA) process for resource-constrained IoT devices. The system achieves end-to-end decentralization and integrity by leveraging blockchain technology for update distribution and transaction logging. Cryptographic assurance is
Research
Abstract This paper presents the design and implementation of a novel USB RAID controller specifically engineered for ARM Single Board Computer (SBC) cluster servers. The innovation addresses significant storage and redundancy limitations inherent in low-power computing clusters by centralizing management of multiple USB-attached drives. This specialized controller provides
Research
Abstract Distributed High-Performance Computing (HPC) platforms face significant challenges in achieving simultaneous high scalability and fine-grained parallelism due to communication and synchronization overhead. This paper introduces a novel architecture and runtime co-design approach leveraging the extensibility of the RISC-V ISA to optimize task management across thousands
Research
Abstract LOFMPL is an open-source framework designed for advanced logic optimization, specifically targeting the challenges presented by extremely large integrated circuits. It utilizes a scalable, two-pronged optimization approach, starting with Maximal Fanout-Free Cone (MFFC)-based hypergraph partitioning for efficient circuit decomposition. Crucially, the framework integrates Reinforcement Learning
Research
Abstract This comprehensive survey analyzes the landscape of hardware-level Quality of Service (QoS) enforcement features, critical for mitigating resource interference in modern multi-core and heterogeneous computing systems. The paper systematically reviews existing technologies, architectural implementations, and diverse use cases ranging from cloud computing to real-time embedded systems.
News
Abstract Qualcomm has announced the strategic acquisition of Ventana Micro Systems, a leading developer of high-performance RISC-V CPU core designs. Ventana specializes in building sophisticated RISC-V solutions primarily targeting the data center, cloud, and enterprise computing markets. This move significantly strengthens Qualcomm's capabilities and commitment
News
Abstract Qualcomm's acquisition of Ventana Micro Systems signifies a substantial, long-term commitment to developing the RISC-V architecture. This strategic investment is designed to complement Qualcomm's existing dominance in the Arm processor market, rather than immediately replace it. The move positions Qualcomm to leverage the
News
Abstract The VEGA AS2161, marketed as the “DHRUV64,” is a significant new development in the RISC-V ecosystem, featuring a 64-bit, dual-core microprocessor architecture. Operating at a respectable 1 GHz clock speed, this chip is designed for performance applications. Crucially, the DHRUV64 highlights India’s increasing capability and
News
Originally published on Google News - RISC-V Qualcomm’s Ventana acquisition points to a long-term RISC-V strategy to complement its Arm lineup Tom's Hardware AI Analysis Key Highlights * Major Acquisition: Qualcomm has acquired Ventana Micro Systems, a prominent developer of high-performance RISC-V cores. * Strategic
News
Abstract LilyGo has introduced the T-Display P4 handheld, a new development device integrating Espressif's powerful ESP32-P4 RISC-V processor. This handheld features a 4.1-inch display, making it suitable for portable interface applications, prototyping, and educational use. The release signals the market readiness and commercialization
Embedded
Abstract The Government of India has launched the DHRUV64 (VEGA AS2161), an indigenous dual-core 64-bit RISC-V microprocessor developed by C-DAC, marking a significant progression in the country's semiconductor efforts. Clocked at 1 GHz, this MPU features the RV64IMAFD instruction set and supports Linux, positioning
Research
Abstract Designing optimal heterogeneous multi-core processors requires navigating an exponentially large Design Space Exploration (DSE) covering core mixes, interconnects, and scheduling policies. This paper introduces a novel, comprehensive DSE framework specifically tailored for highly configurable architectures, such as those based on RISC-V. By integrating hierarchical pruning techniques and
Research
Abstract TEMpesT is a novel empirical testing methodology designed to rigorously verify memory transistency behaviors in modern CPU implementations, specifically targeting the complexities of the RISC-V Weak Memory Ordering (RVWMO) model. The system uses highly tuned litmus tests and architectural observation techniques to detect transient memory state phenomena often
Research
Abstract This paper presents a customized RISC-V core architecture specifically designed for highly efficient and flexible edge inference of mixed-precision quantized Deep Neural Networks (DNNs). The core utilizes specialized instruction set extensions and architectural modifications optimized to handle varied low-bit quantization schemes (e.g., 2-bit, 4-
Research
Abstract This paper presents a pipeline stage resolved timing characterization framework to systematically compare a 32-bit RISC-V processor implemented on a 20 nm FPGA and a 7 nm FinFET ASIC. The analysis demonstrates that while the critical path remains the execution (EX) to memory (MEM) transition in both
Research
Abstract Lyra is a novel heterogeneous RISC-V verification framework that pairs hardware acceleration via an FPGA SoC with an ISA-aware generative model, LyraGen, for processor fuzzing. This methodology enables high-throughput differential checking and generation of semantically rich test stimuli, addressing the limitations of slow software simulation and
Research
Abstract This paper introduces significant improvements in gem5 and gem5 Resources v25.0 to address critical challenges in simulation reproducibility and standardization within computer architecture research. Key innovations include standardizing disk image creation across x86, ARM, and RISC-V using Packer, alongside providing new, validated resources like kernels and benchmarks.
Research
Abstract This survey provides a comprehensive review of the rapidly evolving landscape concerning the integration of Machine Learning (ML) techniques into classical Logic Synthesis workflows. It systematically categorizes various ML applications—ranging from design space exploration and optimization parameter tuning to predicting quality-of-results (QoR)—demonstrating their potential to
News
Originally published on Google News - RISC-V Qualcomm sharpens RISC-V influence with Ventana acquisition DIGITIMES Asia
News
Originally published on Google News - RISC-V Qualcomm sharpens RISC-V influence with Ventana acquisition digitimes
News
Abstract India has launched DHRUV64, a major step in its indigenous semiconductor development, introducing the country's first 64-bit dual-core processor based on the open-source RISC-V architecture. This CPU operates at 1 GHz and signifies a critical move toward technological self-reliance in high-performance
Research
Abstract The paper introduces "svc-hook," a novel framework designed for intercepting and hooking system calls specifically on the ARM64 architecture. This highly effective instrumentation is achieved through the use of aggressive binary rewriting techniques, modifying the executable code directly to divert execution flow. This approach provides a
Research
Originally published on ACM Digital Library Middleware '25: Proceedings of the 26th International Middleware Conference, Page 1-15.
Research
Abstract IM-PIR introduces a novel architectural approach for Private Information Retrieval (PIR) by integrating the computationally intensive cryptographic operations directly into the memory subsystem, effectively addressing the data movement bottleneck known as the memory wall. This In-Memory Private Information Retrieval design significantly reduces query latency and energy consumption
Research
Abstract SoCurity is a novel framework designed to significantly enhance System-on-Chip (SoC) security by implementing robust anomalous activity detection (AAD) at runtime. The innovation focuses not only on identifying security breaches but also on accurately localizing the source of the malicious activity within the complex SoC architecture. This
Research
Abstract HOPPERFISH introduces a novel, robust profiling framework explicitly engineered to address the complexities of modern heterogeneous computing systems. The framework achieves holistic system profiling by offering portable and extensible instrumentation across diverse architectural components, including CPUs, GPUs, and specialized accelerators. This tool aims to simplify performance analysis and debugging
News
Abstract A new handheld device has been unveiled, leveraging the powerful, open-source RISC-V ESP32-P4 microcontroller. This device is highly integrated, featuring a high-quality AMOLED display for interactive user interfaces. Furthermore, the incorporation of LoRa technology enables long-range, low-power wireless communication capabilities, positioning it for
News
Abstract A new RISC-V based platform, branded RT-Europa, has been introduced targeting demanding real-time control applications within the automotive sector. This platform is specifically designed to meet the stringent safety and reliability standards required for modern vehicle systems. The launch signifies a major step in the adoption
Hi! Prof. B is busy in the lab, but I can help check his notes for you! What do you need to know?
