Minimum RISC-V: Maximum FPGA Efficiency

AI Analysis

Abstract

Key Highlights

• Developed a novel application-specific RISC-V optimization method for FPGAs.
• Achieved significant logic reduction (up to 60%) and high clock frequencies (up to 775 MHz) for optimized cores.
• Optimized RISC-V cores are as small as 170 ALMs on Altera Agilex 5 devices.
• Demonstrated deterministic area and performance for multi-core FPGA designs through dense packing.
• Introduced a lightweight, deeply pipelined RISC-V core capable of running above 700 MHz.

Technical Details

• A lightweight RISC-V core was designed with 8-stage and 5-stage pipeline variants, lacking forwarding or hardware interlocks, relying on software NOPs for hazard avoidance.
• The core utilizes Altera M20K memories for Instruction Memory, Register File, and Data Memory, leveraging embedded pipeline stages for efficiency.
• An optimization method compiles the application binary and a specialized processor instance contemporaneously, expanding instructions into an application-specific encoding and removing unused datapath and decode logic.
• The optimization reduced logic size by 50% to 70%, with optimized RV32I cores achieving 170 ALMs and 775 MHz on an Altera Agilex 5 device.
• For RV32F configurations, an additional optimization for enumerated immediate shifts reduced logic by a further 25% by replacing complex shifters with multiplexers.
• Multi-core implementations demonstrated predictable packing, with five constrained cores closing timing at 724 MHz, compared to 784 MHz for unconstrained single cores.

Implications

• The methodology enables the creation of highly efficient and compact RISC-V soft processors, particularly suitable for resource-constrained FPGA applications.
• The application-specific optimization significantly reduces resource usage and improves clock frequency, offering a competitive alternative to general-purpose soft CPUs.
• The ability to pack optimized processors deterministically facilitates predictable multi-core density planning and performance in FPGA-based systems.
• The optimization method is general and can be applied to other processor architectures beyond RISC-V.
• The high clock rates achieved for optimized cores can outweigh increased CPI due to software hazard mitigation, maintaining competitive wall-clock performance.

Limitations

• Optimized cores are assembler-compatible with the original program but are not binary-compatible with a general-purpose RISC-V.
• The lightweight core's lack of forwarding and hardware interlocks necessitates software NOPs, which can increase program size and CPI.
• The research primarily targets single-threaded operation and does not support multi-threaded (FENCE), Control and Status Register (CSR), or operating-system support instructions (ECALL).
• Byte and half-word accesses require multiple instructions and must be enabled as a compiler option.
• The evaluation of the generic RTL core on FPGAs from other vendors was not performed in this work.
• Some benchmarked configurations, such as the RV32M FFT, were explored for application efficiency but did not produce a synthesizable optimized instance.