AI Analysis

Abstract

This paper presents the first comprehensive hardware study of four state-of-the-art randomized cache designs—Ceaser-S, ScatterCache, SassCache, and Mirage—integrated into the last-level cache of a multi-core out-of-order RISC-V System-on-Chip. The research addresses the gap between abstract randomized cache proposals and their practical hardware realization by identifying common and design-specific implementation challenges, such as handling cache skew, IDF integration, and asynchronous operations. Through full FPGA implementations running extensive benchmarks, the study reveals that while pipelining the Index Derivation Function (IDF) is necessary, it is often insufficient to prevent significant processor frequency degradation, which can be up to 35%. The authors demonstrate that critical path redesigns can recover much of this lost frequency, albeit with trade-offs in latency or concurrency. Furthermore, the evaluation shows that increased LLC access latency, rather than additional cache misses, is the primary driver of performance degradation (up to 11% IPC reduction), with resource overheads ranging from 1-14% for ASIC area and 10-35% for FPGA LUTs.

Key Highlights

• First end-to-end hardware implementation and comparative evaluation of four prominent randomized cache designs (Ceaser-S, ScatterCache, SassCache, Mirage) on a multi-core out-of-order RISC-V SoC.
• Identified that pipelining the Index Derivation Function (IDF) alone is insufficient to prevent significant frequency drops in full SoC integration.
• Observed frequency degradation of up to 35% compared to a baseline set-associative cache, with critical paths often outside the IDF.
• Demonstrated that redesigning critical paths can recover most lost frequency (within 10% of baseline) at the cost of increased latency or reduced concurrency.
• Determined that increased Last-Level Cache (LLC) access latency, not additional misses, is the dominant factor for Instructions Per Cycle (IPC) degradation, reducing it by up to 11%.
• Quantified resource overheads: 10-35% increase in FPGA LUTs and 1-14% increase in ASIC area.

Technical Details

• Four randomized cache designs (Ceaser-S, ScatterCache, SassCache, Mirage) were implemented as the Last-Level Cache (LLC) of a multi-core out-of-order NaxRiscv RISC-V SoC.
• Hardware solutions were developed for common challenges including partitioning metadata RAM for skewed caches, refining hazard detection to line-level granularity, and integrating pipelined Index Derivation Functions (IDFs).
• Design-specific solutions include a dedicated relocation Finite-State Machine (FSM) and an extended hazard controller for Ceaser-S, and separated data-pointer arrays and an extended hazard controller for Mirage.
• IDFs used include a two-stage Feistel network for Ceaser-S, a three-stage QARMA pipeline for ScatterCache, a three-stage SassCache permutation, and a three-stage PRINCE pipeline for Mirage.
• Evaluations were performed on complete FPGA implementations (AMD Xilinx VCU118) running SPEC CPU 2017 rate and GAPBS workloads to completion.
• ASIC area estimations used Synopsys Design Compiler with Nangate 45nm standard-cell library and OpenRAM SRAMs.
• Frequency bottlenecks were traced to concurrent-relocation conflict handling (Ceaser-S), placement-and-routing pressure from IDF integration (SassCache), and additional accesses to enlarged metadata RAMs (Mirage).
• Redesigns included disabling concurrent relocation (Ceaser-SF), increasing IDF pipeline depth (SassCacheF), and adding pipeline stages for metadata-RAM response buffering (MirageF).

Implications

• Randomized cache designs, while effective against side-channel attacks, introduce significant hardware implementation challenges beyond just pipelining the IDF.
• The performance overhead of randomized caches is primarily driven by increased LLC access latency rather than higher cache miss rates, necessitating careful pipeline design.
• Achieving high operating frequencies for randomized caches requires design-specific microarchitectural redesigns, often involving trade-offs in concurrency, latency, or pipeline depth.
• Evaluating randomized caches solely through architectural simulators or isolated IDF analysis can significantly underestimate the true performance and frequency costs in a full SoC context.
• The resource overhead for randomized caches, particularly ASIC area, is dominated by additional cache storage rather than control logic.
• Future randomized cache designs must consider full-system integration challenges and their impact on processor frequency and overall execution speed, not just security and IPC.

Limitations

• The study targets an advanced open-source out-of-order RISC-V SoC, but commercial processors may feature larger cache hierarchies, deeper pipelines, and more complex memory systems, which could present different challenges.
• Many other randomized-cache proposals beyond the four studied were not evaluated in hardware.
• The ASIC evaluation was based on post-synthesis results, not a complete physical design flow, which could provide further insights into optimization opportunities and bottlenecks.
• The power analysis is based on Vivado's vector-based analysis flow for FPGA and post-synthesis for ASIC, which are estimations.
• The study uses random replacement for randomized caches, which provides comparable performance but might not be optimal for all designs.
• The NaxRiscv SoC was configured with a single core for frequency analysis, and multicore results were limited to specific benchmarks, which might not fully capture all multicore interactions.

Source: https://arxiv.org/abs/2611.00282