RISC-V LinuxBetaOPEN SILICON. SHARED KNOWLEDGE.

A Mixed-Precision CNN-LSTM Accelerator Featuring Long-Kernel Memory Reuse and Dynamic Quantization for Sleep Staging

AI Analysis Abstract This letter details a mixed-precision CNN-LSTM accelerator designed for EEG-based sleep staging. It incorporates a serpentine dataflow to efficiently process long temporal convolutions, significantly reducing memory accesses compared to conventional methods.…

Figure from the source article: A Mixed-Precision CNN-LSTM Accelerator Featuring Long-Kernel Memory Reuse and Dynamic Quantization for Sleep Staging
Source: arxiv.org

AI Analysis

Abstract

This letter details a mixed-precision CNN-LSTM accelerator designed for EEG-based sleep staging. It incorporates a serpentine dataflow to efficiently process long temporal convolutions, significantly reducing memory accesses compared to conventional methods. A hybrid quantization scheme, combining runtime dynamic quantization for recurrent layers and layer-by-layer mixed precision, effectively shrinks the model size while preserving inference accuracy. The accelerator, fabricated in 65nm CMOS, integrates a bit-flexible MAC architecture and channel-grouped memory scheduling to support INT2/4/8/16 inference. It demonstrates substantial speedup over a RISC-V processor and maintains high accuracy on the MASS-SS3 dataset, making it suitable for energy-efficient wearable applications.

Key Highlights

  • A mixed-precision CNN-LSTM accelerator specifically designed for EEG-based sleep staging.
  • Introduces a serpentine dataflow that reduces memory accesses by 6.2x for long temporal convolutions.
  • Employs a hybrid static-dynamic mixed-precision quantization scheme, reducing model size by 4.16x.
  • Features a bit-flexible MAC architecture and channel-grouped memory scheduling supporting INT2/4/8/16 inference.
  • Achieves a 258x speedup over an iso-frequency 32b RISC-V processor.
  • Consumes 0.40mW average power and maintains 5-class accuracy within 0.15% of the floating-point baseline.
  • Demonstrates 95.75% N3 sensitivity when optimized for deep-sleep detection.

Technical Details

  • The accelerator is fabricated in 65nm CMOS technology.
  • A serpentine dataflow propagates activations between neighboring processing elements, reducing memory accesses by 6.2x compared to output-stationary and 2.25x compared to weight-stationary dataflows for long CNN kernels.
  • A hybrid quantization scheme applies runtime dynamic quantization to LSTM and MLP layers and assigns mixed precision (INT2/4/8/16) on a layer-by-layer basis.
  • The bit-flexible multiplier accepts two 16b inputs and can execute eight 2b, four 4b, two 8b, or one 16b multiplication in parallel.
  • Channel-grouped memory scheduling packs multiple channels into each 16b memory word to maximize bandwidth utilization and eliminate cross-word remapping.
  • The accelerator consumes an average of 0.40mW at 8MHz and 1V supply, with inference taking 2.47s for a 30s EEG epoch.
  • It achieves a peak power efficiency of 635 GOPS/W during 2b operation at 0.55V.
  • The model size is reduced by 4.16x due to the mixed-precision approach.
  • The architecture includes an 8-PE array, with two Super PEs integrating pooling, activation, and quantization functions.
  • Total on-chip memory capacity is 1.8 KB.

Implications

  • Enables energy-efficient local deep learning inference on wearable EEG sensors, reducing latency and wireless transmission energy.
  • Supports precise deep sleep (N3 stage) detection, which is crucial for sleep-stage-specific auditory stimulation and enhancing sleep quality.
  • Addresses the challenge of demanding deep learning workloads within sub-milliwatt power budgets for sustained overnight monitoring with small batteries.
  • The developed techniques are broadly applicable to other EEG-based deep learning workloads beyond sleep staging.
  • Offers a hardware solution for long convolutional kernels, which are common in EEG analysis but poorly supported by conventional accelerators.

Limitations

  • The letter focuses exclusively on the deep learning accelerator, not the broader sleep modulation System-on-Chip (SoC) in which it was initially introduced.
  • Numerical accuracy comparisons with other sleep-staging designs should be interpreted considering variations in input configuration, classification settings, and evaluation protocols across studies.
  • The power consumption of 0.40mW is an average over a 30-second inference interval, not a continuous power draw.
  • The speedup benchmark is against a specific iso-frequency, single-core 32b RISC-V processor with a four-stage pipeline, which may not represent all possible processor baselines.

Source: https://arxiv.org/abs/2611.00660