Archive

Proceedings of the 15th ACM SIGPLAN International Conference on Certified Programs and Proofs

Abstract The Proceedings of the 15th ACM SIGPLAN CPP '26 compile cutting-edge research focused on the intersection of formal verification and practical program development. This conference showcases innovations in...

Proceedings of the 12th International Conference on Next Generation Computing, Communication, Systems and Security

Abstract The Proceedings of the 12th International Conference on Next Generation Computing, Communication, Systems and Security (NSysS '25) compiles cutting-edge research focused on the convergence of advanced digital technologies....

Proceedings of the 37th Australian Conference on Human-Computer Interaction

Abstract The Proceedings of the 37th Australian Conference on Human-Computer Interaction (OzCHI '25) collects pivotal research focused on advancing user experience, interface design, and interaction methodologies for emerging technologies....

Linux Patches Enable Intel GPU Firmware Updating From Non-x86 Systems

Abstract New Linux patches are enabling Intel discrete GPU firmware updates on non-x86 architectures, such as ARM and RISC-V. Previously, this functionality was restricted because the Intel Management Engine Interface...

MUSE Book laptop review – Testing an octa-core RISC-V Linux laptop in 2026 - CNX Software

Abstract The article provides a review of the MUSE Book, an octa-core RISC-V laptop running Linux, focusing on its performance and viability in the projected 2026 computing landscape. This testing...

MUSE Book laptop review – Testing an octa-core RISC-V Linux laptop in 2026

Abstract The MUSE Book RISC-V laptop, featuring the SpacemiT K1/M1 octa-core SoC, demonstrates the maturation of the RISC-V hardware ecosystem into a consumer form factor. The 2026 review specifically...

Nice to Meet You: Synthesizing Practical MLIR Abstract Transformers

Abstract This work introduces a novel approach for synthesizing practical Abstract Transformers tailored for the MLIR compiler infrastructure. By automating the generation of these crucial components, the system significantly reduces...

ChiSA: Static Analysis for Lightweight Chisel Verification

Abstract ChiSA introduces a novel static analysis framework specifically designed for lightweight verification of hardware designs written in the Chisel HDL. This approach allows developers to detect common design errors,...

ArchSem: Reusable Rigorous Semantics of Relaxed Architectures

Abstract ArchSem introduces a novel, reusable framework for defining the rigorous semantics of complex relaxed computer architectures. This approach allows developers and verification engineers to formally specify weak memory models...

Foundational Verification of Running-Time Bounds for Interactive Programs

Abstract This article introduces a novel methodology for the foundational verification of running-time bounds, specifically addressing the complexities of interactive programs. It establishes a formal framework capable of mathematically certifying...

RISC-V's rise: A third CPU ecosystem in 5-10 years? - digitimes

Abstract The Digitimes article assesses the rapid expansion of the RISC-V Instruction Set Architecture (ISA) in the global semiconductor market. It hypothesizes that, based on current industry trends and accelerated...

RISC-V’s AI Revolution: SiFive’s 2nd Gen Intelligence Cores Set to Topple the ARM/x86 Duopoly - FinancialContent

Abstract SiFive has introduced its 2nd Generation Intelligence Cores, significantly accelerating the RISC-V movement into the high-performance computing and AI processing markets. These advanced cores are specifically designed to handle...

Meta and Qualcomm push RISC-V market share towards 25% ... - eeNews Europe

Abstract Major technology leaders Meta and Qualcomm are aggressively integrating RISC-V into their semiconductor strategies, validating the open-source instruction set architecture (ISA). This strategic push is projected to propel RISC-V&...

RISC-V Hits 25% Market Share: The Rise of Open-Source Silicon Sovereignty

Abstract The RISC-V instruction set architecture (ISA) has achieved a significant milestone, claiming roughly 25% of the global processor market share. This rapid adoption is driven by its open, modular...

RISC-V hits 25% market penetration thanks to Meta and Qualcomm - Adafruit

Abstract The RISC-V open-source architecture has achieved a significant milestone, reaching 25% market penetration in relevant sectors. This substantial growth is primarily driven by massive adoption and investment from major...

Andrew “bunnie” Huang designs a “mostly open” RISC-V board - Adafruit

Abstract Andrew “bunnie” Huang has designed a new RISC-V development board characterized by its commitment to a “mostly open” hardware philosophy. This project leverages the royalty-free RISC-V architecture to create...

The RISC-V Revolution: Qualcomm’s Acquisition of Ventana Micro Systems Signals the End of the ARM-x86 Duopoly - FinancialContent

Abstract Qualcomm’s acquisition of Ventana Micro Systems marks a pivotal moment, validating the RISC-V architecture's readiness to compete in high-performance computing markets traditionally dominated by ARM and...

U.S. must guard NASA’s future as China eyes space dominance | Opinion - Florida Today

Abstract This opinion piece highlights the escalating geopolitical rivalry between the United States (NASA) and China for supremacy in space exploration, warning that China is aggressively pursuing space dominance. The...

Nordic Semi nRF54LM20B wireless SoC integrates 128 MHz Axon NPU for Edge AI workloads

Abstract Nordic Semiconductor has introduced the nRF54LM20B wireless SoC, the first nRF54L microcontroller to integrate a dedicated 128 MHz Axon Neural Processing Unit (NPU) for high-efficiency edge AI tasks. This...

Espressif Systems showcases ESP32-E22 Wi-Fi 6E SoC and ESP32-H21 BLE MCU for battery-powered devices

Abstract Espressif Systems showcased two new RISC-V microcontrollers at CES 2026: the high-performance ESP32-E22 Wi-Fi 6E SoC and the ultra-low-power ESP32-H21 Bluetooth LE MCU. The ESP32-E22 features a dual-core 500...

Openterface KVM-GO – An ultra-compact KVM-over-USB solution with HDMI, DP, or VGA video input

Abstract The Openterface KVM-GO is an ultra-compact, open-source KVM-over-USB solution designed for troubleshooting headless devices and remote server monitoring. This keychain-sized gadget, powered by a WCH CH32V208 RISC-V MCU, features...

Allwinner V861 dual-core 64-bit RISC-V AI Camera SiP features 128MB DDR3L, 4K H.265/H.264 video encoder - CNX Software

Abstract Allwinner has introduced the V861, a new dual-core 64-bit RISC-V System-in-Package (SiP) specifically designed for advanced AI camera applications. This chip integrates 128MB of DDR3L memory directly, significantly simplifying...

Allwinner V861 dual-core 64-bit RISC-V AI Camera SiP features 128MB DDR3L, 4K H.265/H.264 video encoder

Abstract The Allwinner V861 is a new dual-core 64-bit RISC-V SiP optimized for 4K AI camera applications, notably integrating 128MB DDR3L and a 1 TOPS NPU. It utilizes XuanTie C907...

WCH CH32H417 dual-core RISC-V MCU offers USB 3.0, 500MB/s UHSIF, and Fast Ethernet interfaces - CNX Software

Abstract WCH has announced the CH32H417, a new dual-core RISC-V MCU designed for high-speed data handling in embedded systems. The key innovation is the integration of advanced connectivity features, including...

WCH CH32H417 dual-core RISC-V MCU offers USB 3.0, 500MB/s UHSIF, and Fast Ethernet interfaces

Abstract The WCH CH32H417 is a newly released dual-core RISC-V microcontroller featuring primary cores clocked up to 400 MHz and substantial integrated memory (960 KB Flash/896 KB SRAM). Its...

I-COR: Instruction-Level Fault Tolerance for Register File in 3-Stage Pipeline RISC-V Processors

Abstract I-COR is a novel instruction-level fault tolerance mechanism specifically designed to protect the Register File (RF) in simple 3-stage pipeline RISC-V processors. This approach leverages instruction context to selectively...

VisionFive 2 Lite SBC Review – Ubuntu 24.04 on a low-cost RISC-V SBC in 2026

Abstract This 2026 review of the low-cost StarFive VisionFive 2 Lite SBC, based on the JH7110S RISC-V SoC, demonstrates significant maturation in the platform’s core Linux support by successfully...

DFRobot HUSKYLENS 2 AI camera review – From built-in AI samples to training a custom model to detect elephants

Abstract The DFRobot HUSKYLENS 2 is a next-generation AI vision sensor leveraging a Kendryte K230 dual-core RISC-V SoC paired with a potent 6 TOPS AI accelerator, ensuring fast, low-latency, on-device...

Bit-Brick Cluster K1 lets you build a 32-core RISC-V computer (by clustering 4 SpacemiT K1 boards) - Liliputing

Abstract The Bit-Brick Cluster K1 introduces a new solution for creating powerful, multi-core RISC-V computers through modular assembly. This system achieves a 32-core configuration by physically clustering four individual SpacemiT...

Lingshuo Technology Secures Angel Funding, Focuses on Automotive-Grade RISC-V Chips - Pandaily

Abstract Lingshuo Technology successfully secured Angel funding to accelerate its mission of developing specialized automotive-grade chips utilizing the RISC-V architecture. This investment underscores growing confidence in the RISC-V ecosystem'...

Ethereum’s RISC-V Pivot: Vitalik Buterin Reveals Why eWASM Was Abandoned - Blockonomi

Abstract Ethereum co-founder Vitalik Buterin announced that the platform is pivoting away from the previously planned eWASM (Ethereum WebAssembly) execution environment. The project is instead focusing on adopting the open-source...

Why Ethereum Abandoned eWASM for RISC-V Architecture - Live Bitcoin News

Abstract The technical article reports on a significant architectural pivot within the Ethereum ecosystem, announcing the abandonment of the previously planned eWASM (Ethereum WebAssembly) virtual machine standard. Ethereum is instead...

Bit-Brick Cluster K1 – A 4-slot RISC-V cluster board for SpacemiT K1-based SSOM-K1 system-on-module - CNX Software

Abstract The Bit-Brick Cluster K1 is a new 4-slot RISC-V cluster board designed to utilize the SpacemiT K1-based SSOM-K1 system-on-module, enabling compact, multi-node computing. This platform facilitates the development and...

Bit-Brick Cluster K1 – A 4-slot RISC-V cluster board for SpacemiT K1-based SSOM-K1 system-on-module

Abstract The Bit-Brick Cluster K1 is a specialized cluster board designed to house up to four SSOM-K1 system-on-modules, powered by the SpacemiT K1 octa-core RISC-V processor optimized for high-performance edge...

ESP32-C6 development board features 1.8-inch AMOLED touch display, built-in mic and speaker, IMU, RTC, and more

Abstract Waveshare introduces the ESP32-C6-Touch-AMOLED-1.8, a compact development board leveraging the ESP32-C6 SoC, which features a single-core 32-bit RISC-V CPU and comprehensive wireless connectivity including Wi-Fi 6, Bluetooth 5...

M5Stack NanoH2 – An ultra-compact ESP32-H2 IoT development kit with Zigbee, Thread, and Matter connectivity

Abstract The M5Stack NanoH2 is an ultra-compact, standalone IoT development kit built around the Espressif ESP32-H2 system-on-chip, specifically optimized for smart home applications. It provides critical multi-protocol wireless connectivity, natively...

RISC-V Hits 25% Market Penetration as Qualcomm and Meta Lead the Shift to Open-Source Silicon - FinancialContent

Abstract RISC-V has reached a critical adoption milestone, achieving 25% market penetration across the silicon industry. This significant growth is spearheaded by major technology firms, specifically citing Qualcomm and Meta,...

German Chip developer TASKING joins open RISC-V automotive alliance - Telematics Wire

Abstract The German chip development tools company, TASKING, has joined the open RISC-V automotive alliance, signaling increased industry commitment to the open-standard architecture within the vehicle technology sector. This membership...

The ARM Killer? Jim Keller’s Tenstorrent Unleashes Ascalon RISC-V IP to Disrupt the Data Center - FinancialContent

Abstract Tenstorrent, led by legendary chip architect Jim Keller, has announced the launch of Ascalon, a new high-performance RISC-V processor intellectual property (IP) core. This powerful new design is explicitly...

Top 10 articles of 2025 - embedded.com

Abstract The article compilation titled 'Top 10 articles of 2025' from embedded.com likely serves as a critical retrospective, reviewing the year's most significant technological advancements...

RISC-V’s Rise: The Open-Source Alternative Challenging ARM’s Dominance - FinancialContent

Abstract The RISC-V ISA is emerging as the premier open-source alternative, directly challenging ARM's historical dominance in the chip industry. Its key advantages include flexibility, royalty-free licensing, and...

Partnership Drives RISC-V Adoption in Automotive - embedded.com

Abstract A new strategic partnership has been formed specifically to accelerate the integration and validation of the RISC-V instruction set architecture within the automotive industry. This collaboration addresses the stringent...

Qualcomm's Xqci RISC-V Extension Now Deemed Non-Experimental For LLVM 22

Abstract Qualcomm's proprietary Xqci RISC-V vendor extension has officially transitioned from experimental status to stable within the LLVM compiler toolchain. This critical change was recently committed to the...

From Tiny Machine Learning to Tiny Deep Learning: A Survey

Abstract This survey paper meticulously tracks the technological progression from traditional Tiny Machine Learning (TinyML) to the sophisticated deployment of Tiny Deep Learning (TinyDL) on highly resource-constrained edge devices. It...

Parrot 7.0 Ethical Hacking Distro Released with KDE Plasma, RISC-V Support - 9to5Linux

Abstract Parrot OS 7.0, the specialized ethical hacking and security distribution, has been officially released with significant updates. This version introduces support for the KDE Plasma desktop environment, offering...

Qualcomm's Xqci RISC-V Extension Now Deemed Non-Experimental For LLVM 22 - Phoronix

Abstract Qualcomm's specialized Xqci extension for RISC-V architecture has been officially designated as non-experimental within the upcoming LLVM 22 compiler infrastructure release. This transition signifies the maturity and...

Power Side-Channel Analysis of the CVA6 RISC-V Core at the RTL Level Using VeriSide

Abstract This paper investigates the security of the CVA6 RISC-V core against power side-channel attacks by employing an RTL-level power profiling framework called VeriSide. The analysis targeted a software-based AES...

The Great Architecture Pivot: How RISC-V Became the Global Hedge Against Geopolitical Volatility and Licensing Wars - FinancialContent

Abstract RISC-V is fundamentally shifting the semiconductor landscape, becoming a global hedge against pervasive geopolitical volatility and restrictive licensing wars. This 'Great Architecture Pivot' is driven by the...

On-Demand Regular Expression Matching on FPGAs for Efficient Deep Packet Inspection

Abstract This work introduces a novel 'On-Demand' architecture for regular expression matching implemented on FPGAs, specifically designed to maximize efficiency in Deep Packet Inspection (DPI) environments. The key...

GigaDevice GD32VW553-UNIFI – A $2+ WiFi 6 and Bluetooth 5.2 LE wireless IoT module - CNX Software

Abstract GigaDevice has unveiled the GD32VW553-UNIFI, a highly cost-effective wireless IoT module leveraging the RISC-V architecture and priced aggressively around $2. This module integrates cutting-edge connectivity, featuring both WiFi 6...

GigaDevice GD32VW553-UNIFI – A $2+ WiFi 6 and Bluetooth 5.2 LE wireless IoT module

Abstract The GigaDevice GD32VW553-UNIFI is a new, highly competitive wireless IoT module based on an integrated GD32VW553 RISC-V microcontroller, available at an ultra-low price point of approximately $2+. This module...

A Brief History of Computing with Real Numbers, Part 2: A Revolutionary New Approach

Abstract This article, the second in a historical series, critiques the persistent limitations and error propagation issues inherent in traditional IEEE 754 floating-point standards. It introduces a 'revolutionary new...

Arm stock declines massively as Qualcomm acquires RISC-V designer Ventana Micro - TechRadar

Abstract Qualcomm's acquisition of RISC-V chip designer Ventana Micro marks a significant shift in the competitive landscape of processor IP. This strategic move immediately caused a sharp decline...

XIAO Soil Moisture Sensor review with Home Assistant

Abstract Seeed Studio launched the XIAO Soil Moisture Sensor, an ultra-low power device powered by the XIAO ESP32C6 module utilizing dual RISC-V cores for extended battery life on a single...

5 open-source projects I’ll happily open my wallet for - How-To Geek

Abstract The How-To Geek article presents a curated list of five indispensable open-source projects that the author advocates for financially supporting. This editorial piece highlights the importance of user donations...

PermuteV: A Performant Side-channel-Resistant RISC-V Core Securing Edge AI Inference

Abstract PermuteV is a performant side-channel resistant RISC-V core designed to secure Edge AI inference models against physical attacks, which frequently expose confidential neural network data. The core employs a...

ESP32-P4 learning and prototyping kit features 7-inch touchscreen, comes with 16 modules and AI lessons

Abstract Elecrow has launched the "All-in-One Starter Kit for ESP32-P4," an open-source learning and prototyping platform built around the dual-core RISC-V ESP32-P4 chip. This comprehensive kit features a...

Raspberry Pi RP2350 devkit features 1.85-inch round touch display, microphone, optional speaker and battery box

Abstract Waveshare has introduced the RP2350-Touch-LCD-1.85C devkit, built around the new Raspberry Pi RP2350A microcontroller, which features a 1.85-inch round touchscreen and integrated audio capabilities for HMI solutions....

Call for Presentations: RISC-V for Embedded, AI, and Automotive ... - eeNews Europe

Abstract eeNews Europe has issued a specialized Call for Presentations (CfP) centered on advancing the implementation and ecosystem of the open-standard RISC-V architecture. The invitation targets proposals showcasing cutting-edge developments...

Announcing the 2025 AI & RISC-V Gemini Credit Recipients

Abstract RISC-V International announced the recipients of the 2025 AI & RISC-V Gemini Credit grants, a program designed to leverage AI models to significantly accelerate the RISC-V software ecosystem. Recipients...

Intel ISPC 1.29 Drops Gen9 GPU Targets, Add New Optimizations & Experimental RISC-V - Phoronix

Abstract Intel has released version 1.29 of its Implicit SPMD Program Compiler (ISPC), marking a significant update that focuses on modernization and architecture expansion. The release notably discontinues support...

A Brief History of Formal Methods in China

Abstract This article details the historical trajectory and evolution of formal methods (FM) research and practical application within the technological landscape of China. It chronicles key academic milestones, influential research...

RISC-V vs. Arm & x86: AI Drives Open-Source Chip Shift | 2025 Analysis - News and Statistics - IndexBox

Abstract The analysis forecasts a significant open-source chip shift driven by AI acceleration, positioning the customizable RISC-V architecture as a powerful challenger to established proprietary instruction sets like Arm and...

Newer RISC-V CPUs Vulnerable To Spectre V1 - Linux Mitigation Patches Posted - Phoronix

Abstract Newer, high-performance RISC-V CPUs have been confirmed vulnerable to the classic Spectre Variant 1 (V1) speculative execution side-channel attack. This discovery highlights that RISC-V implementations adopting modern performance features,...

ChatArch: A Knowledge-driven Graph-of-thought LLM Framework for Processor Architecture Optimization

Abstract ChatArch introduces a novel Knowledge-driven Graph-of-thought (GoT) LLM framework designed to automate and optimize the challenging process of processor architecture design. By integrating domain-specific knowledge graphs, ChatArch facilitates structured,...

Co-emulation platform targets complex RISC-V chip design - Engineering.com

Abstract A newly introduced co-emulation platform is specifically engineered to handle the high complexity and customizability inherent in advanced RISC-V chip designs. This verification solution integrates high-speed hardware emulation with...

Co-emulation platform targets complex RISC-V chip design - Engineering.com

Abstract A newly introduced co-emulation platform is specifically engineered to handle the high complexity and customizability inherent in advanced RISC-V chip designs. This verification solution integrates high-speed hardware emulation with...

Tenstorrent advances RISC-V AI chips in China with former Arm China CEO - DIGITIMES Asia

Originally published on Google News - RISC-V Tenstorrent advances RISC-V AI chips in China with former Arm China CEO  DIGITIMES Asia...

SiFive and IAR strengthen RISC-V automotive toolchain ... - eeNews Europe

Abstract SiFive and IAR Systems have announced a collaboration aimed at significantly enhancing the RISC-V automotive toolchain. This partnership integrates IAR's certified Embedded Workbench with SiFive's...

Tenstorrent advances RISC-V AI chips in China with former Arm China CEO - digitimes

Abstract Tenstorrent is strategically advancing its RISC-V AI chip initiative within the crucial Chinese market. This expansion is bolstered by the involvement of the former CEO of Arm China, signaling...

India unveils a homegrown dual-core 1GHz RISC-V processor, the DHRUV64 - theregister.com

Abstract India has unveiled the DHRUV64, an indigenously developed dual-core processor utilizing the open-source RISC-V architecture. This chip operates at a clock speed of 1GHz, signaling a major step toward...

Breakingviews - AI’s 2026 dark horse will be open-standard chips - Reuters

Abstract The Reuters Breakingviews article predicts that open-standard chips, most notably those based on architectures like RISC-V, will emerge as the unexpected 'dark horse' in the AI hardware...

Quantum-Resistant FOTA: End-to-End Decentralized Firmware Updates for IoT Using Blockchain and CRYSTALS-Dilithium

Abstract This paper presents a novel, quantum-resistant (QR) firmware update architecture designed to secure the critical Firmware Over-The-Air (FOTA) process for resource-constrained IoT devices. The system achieves end-to-end decentralization and...

Design of a USB RAID Controller for ARM SBC cluster server

Abstract This paper presents the design and implementation of a novel USB RAID controller specifically engineered for ARM Single Board Computer (SBC) cluster servers. The innovation addresses significant storage and...

Towards high scalability and fine-grained parallelism on distributed HPC platforms

Abstract Distributed High-Performance Computing (HPC) platforms face significant challenges in achieving simultaneous high scalability and fine-grained parallelism due to communication and synchronization overhead. This paper introduces a novel architecture and...

LOFMPL: An Open-source Logic Optimization Framework with MFFC-based Hypergraph Partition and Reinforcement Learning for Large Circuits

Abstract LOFMPL is an open-source framework designed for advanced logic optimization, specifically targeting the challenges presented by extremely large integrated circuits. It utilizes a scalable, two-pronged optimization approach, starting with...

Hardware-Level QoS Enforcement Features: Technologies, Use Cases, and Research Challenges

Abstract This comprehensive survey analyzes the landscape of hardware-level Quality of Service (QoS) enforcement features, critical for mitigating resource interference in modern multi-core and heterogeneous computing systems. The paper systematically...

Qualcomm acquires Ventana Micro Systems - Evertiq

Abstract Qualcomm has announced the strategic acquisition of Ventana Micro Systems, a leading developer of high-performance RISC-V CPU core designs. Ventana specializes in building sophisticated RISC-V solutions primarily targeting the...

Qualcomm’s Ventana acquisition points to a long-term RISC-V strategy to complement its Arm lineup - Tom's Hardware

Abstract Qualcomm's acquisition of Ventana Micro Systems signifies a substantial, long-term commitment to developing the RISC-V architecture. This strategic investment is designed to complement Qualcomm's existing...

VEGA AS2161 “DHRUV64” – A 1GHz dual-core 64-bit RISC-V microprocessor designed in India - CNX Software

Abstract The VEGA AS2161, marketed as the “DHRUV64,” is a significant new development in the RISC-V ecosystem, featuring a 64-bit, dual-core microprocessor architecture. Operating at a respectable 1 GHz clock...

Qualcomm’s Ventana acquisition points to a long-term RISC-V strategy to complement its Arm lineup - Tom's Hardware

Originally published on Google News - RISC-V Qualcomm’s Ventana acquisition points to a long-term RISC-V strategy to complement its Arm lineup  Tom's Hardware AI Analysis Key Highlights...

LilyGo T-Display P4 handheld has an ESP32-P4 RISC-V processor and a 4.1 inch display - Liliputing

Abstract LilyGo has introduced the T-Display P4 handheld, a new development device integrating Espressif's powerful ESP32-P4 RISC-V processor. This handheld features a 4.1-inch display, making it suitable...

VEGA AS2161 “DHRUV64” – A 1GHz dual-core 64-bit RISC-V microprocessor designed in India

Abstract The Government of India has launched the DHRUV64 (VEGA AS2161), an indigenous dual-core 64-bit RISC-V microprocessor developed by C-DAC, marking a significant progression in the country's semiconductor...

Toward Comprehensive Design Space Exploration on Heterogeneous Multi-core Processors

Abstract Designing optimal heterogeneous multi-core processors requires navigating an exponentially large Design Space Exploration (DSE) covering core mixes, interconnects, and scheduling policies. This paper introduces a novel, comprehensive DSE framework...

TEMpesT: Testing Empirically for Memory Transistency

Abstract TEMpesT is a novel empirical testing methodology designed to rigorously verify memory transistency behaviors in modern CPU implementations, specifically targeting the complexities of the RISC-V Weak Memory Ordering (RVWMO)...

Efficient Flexible Edge Inference for Mixed-Precision Quantized DNN using Customized RISC-V Core

Abstract This paper presents a customized RISC-V core architecture specifically designed for highly efficient and flexible edge inference of mixed-precision quantized Deep Neural Networks (DNNs). The core utilizes specialized instruction...

Pipeline Stage Resolved Timing Characterization of FPGA and ASIC Implementations of a RISC V Processor

Abstract This paper presents a pipeline stage resolved timing characterization framework to systematically compare a 32-bit RISC-V processor implemented on a 20 nm FPGA and a 7 nm FinFET ASIC....

Lyra: A Hardware-Accelerated RISC-V Verification Framework with Generative Model-Based Processor Fuzzing

Abstract Lyra is a novel heterogeneous RISC-V verification framework that pairs hardware acceleration via an FPGA SoC with an ISA-aware generative model, LyraGen, for processor fuzzing. This methodology enables high-throughput...

Reproducibility and Standardization in gem5 Resources v25.0

Abstract This paper introduces significant improvements in gem5 and gem5 Resources v25.0 to address critical challenges in simulation reproducibility and standardization within computer architecture research. Key innovations include standardizing...

A Survey of Machine Learning Approaches in Logic Synthesis

Abstract This survey provides a comprehensive review of the rapidly evolving landscape concerning the integration of Machine Learning (ML) techniques into classical Logic Synthesis workflows. It systematically categorizes various ML...

Qualcomm sharpens RISC-V influence with Ventana acquisition - DIGITIMES Asia

Originally published on Google News - RISC-V Qualcomm sharpens RISC-V influence with Ventana acquisition  DIGITIMES Asia...

Qualcomm sharpens RISC-V influence with Ventana acquisition - digitimes

Originally published on Google News - RISC-V Qualcomm sharpens RISC-V influence with Ventana acquisition  digitimes...

India Launches DHRUV64, Its First 1 GHz, 64-bit Dual-Core RISC-V CPU - TechPowerUp

Abstract India has launched DHRUV64, a major step in its indigenous semiconductor development, introducing the country's first 64-bit dual-core processor based on the open-source RISC-V architecture. This CPU...

svc-hook: hooking system calls on ARM64 by binary rewriting

Abstract The paper introduces "svc-hook," a novel framework designed for intercepting and hooking system calls specifically on the ARM64 architecture. This highly effective instrumentation is achieved through the...

Recipe: Hardware-Accelerated Replication Protocols

Originally published on ACM Digital Library Middleware '25: Proceedings of the 26th International Middleware Conference, Page 1-15....

IM-PIR: In-Memory Private Information Retrieval

Abstract IM-PIR introduces a novel architectural approach for Private Information Retrieval (PIR) by integrating the computationally intensive cryptographic operations directly into the memory subsystem, effectively addressing the data movement bottleneck...

SoCurity: Enhancing SoC Security with Anomalous Activity Detection and Localization

Abstract SoCurity is a novel framework designed to significantly enhance System-on-Chip (SoC) security by implementing robust anomalous activity detection (AAD) at runtime. The innovation focuses not only on identifying security...

HOPPERFISH: Holistic Profiling with Portable Extensible and Robust Framework Intended for Systems with Heterogeneity

Abstract HOPPERFISH introduces a novel, robust profiling framework explicitly engineered to address the complexities of modern heterogeneous computing systems. The framework achieves holistic system profiling by offering portable and extensible...

RISC-V-based ESP32-P4 handheld integrates AMOLED display and LoRa - LinuxGizmos.com

Abstract A new handheld device has been unveiled, leveraging the powerful, open-source RISC-V ESP32-P4 microcontroller. This device is highly integrated, featuring a high-quality AMOLED display for interactive user interfaces. Furthermore,...

RISC-V automotive platform targets real-time control with RT-Europa - eeNews Europe

Abstract A new RISC-V based platform, branded RT-Europa, has been introduced targeting demanding real-time control applications within the automotive sector. This platform is specifically designed to meet the stringent safety...