RISC-V

Research

What’s on tap from RISC-V in 2025? - Jon Peddie Research

Abstract The analysis from Jon Peddie Research forecasts the critical trends and commercial trajectory of the RISC-V architecture expected throughout 2025. It predicts a significant push beyond embedded systems, focusing on higher-performance segments

By Admin 24 Feb 2025 • 2 min read •

Research

What’s on tap from RISC-V in 2025? - Jon Peddie

Abstract The analysis by Jon Peddie forecasts the significant technological advancements and market shifts anticipated within the RISC-V ecosystem through 2025. The article highlights the architecture's accelerated push into mainstream computing,

By Admin 24 Feb 2025 • 2 min read •

Research

A Novel Approach to Reducing Testing Costs and Minimizing Defect Escapes Using Dynamic Neighborhood Range and Shapley Values (Full Report)

By Admin 12 Feb 2025 •

Research

A Novel Approach to Reducing Testing Costs and Minimizing Defect Escapes Using Dynamic Neighborhood Range and Shapley Values

Abstract This article presents a novel verification methodology aimed at substantially reducing hardware testing costs while simultaneously minimizing defect escapes. The approach integrates Dynamic Neighborhood Range (DNR) algorithms for efficient adaptive test generation

By Admin 12 Feb 2025 • 2 min read •

ISRO and IIT Madras jointly develop indigenous semiconductor chip for space-based applications - The Indian Express (Full Report)

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Research

ISRO and IIT Madras jointly develop indigenous semiconductor chip for space-based applications - The Indian Express (Full Report)

By Admin 12 Feb 2025 •

Research

ISRO and IIT Madras jointly develop indigenous semiconductor chip for space-based applications - The Indian Express

Abstract ISRO and IIT Madras have jointly announced the successful development of an indigenous semiconductor chip designed specifically for space-based applications. This strategic collaboration aims to significantly advance India's self-reliance in

By Admin 12 Feb 2025 • 2 min read •

Research

Mixed-Level Modeling and Evaluation of a Cache-less Grid of Processing Cells (Full Report)

By Admin 19 Dec 2024 •

Research

Mixed-Level Modeling and Evaluation of a Cache-less Grid of Processing Cells

Abstract This article introduces a novel architecture based on a cache-less grid composed of numerous processing cells, designed to maximize parallelism and efficiency for embedded applications. The core innovation lies in utilizing a

By Admin 19 Dec 2024 • 2 min read •

Research

White paper on RISC-V market insights - Jon Peddie (Full Report)

By Admin 19 Nov 2024 •

🔒 Members

Research

What’s on tap from RISC-V in 2025? - Jon Peddie Research

What’s on tap from RISC-V in 2025? - Jon Peddie

A Novel Approach to Reducing Testing Costs and Minimizing Defect Escapes Using Dynamic Neighborhood Range and Shapley Values (Full Report)

A Novel Approach to Reducing Testing Costs and Minimizing Defect Escapes Using Dynamic Neighborhood Range and Shapley Values

ISRO and IIT Madras jointly develop indigenous semiconductor chip for space-based applications - The Indian Express (Full Report)

ISRO and IIT Madras jointly develop indigenous semiconductor chip for space-based applications - The Indian Express

Mixed-Level Modeling and Evaluation of a Cache-less Grid of Processing Cells (Full Report)

Mixed-Level Modeling and Evaluation of a Cache-less Grid of Processing Cells

White paper on RISC-V market insights - Jon Peddie (Full Report)

White paper on RISC-V market insights - Jon Peddie Research (Full Report)

Updates: Past TMT Predictions’ greatest hits and (near) misses - Deloitte (Full Report)

White paper on RISC-V market insights - Jon Peddie Research

RISC-V & Linux

Prof. B's Student