RISC-V

News

SiFive Unleashes Second-Generation RISC-V IP - EE Times

Abstract SiFive has officially unveiled its second generation of commercial RISC-V processor IP, marking a significant increase in performance and features aimed at high-demand markets. This new IP targets sophisticated applications, including data

By Admin 8 Sep 2025 • 2 min read •

News

SiFive Expands Its RISC-V Intelligence Family To Address Exploding AI Workloads - Forbes

Abstract SiFive announced a significant expansion of its RISC-V Intelligence processor family, specifically designed to meet the intensive computational demands of rapidly exploding AI workloads. This strategic launch provides chip designers with highly

By Admin 8 Sep 2025 • 2 min read •

News

Chip designer SiFive aims to cram more RISC-V cores into AI chips - theregister.com

Abstract Chip designer SiFive is strategically focusing its intellectual property (IP) development on high-performance artificial intelligence (AI) accelerators by aiming to significantly increase the density of RISC-V cores. This initiative seeks to leverage

By Admin 8 Sep 2025 • 2 min read •

News

RISC-V Zalasr Support Now Under Review For The Linux Kernel - Phoronix (Full Report)

By Admin 5 Sep 2025 •

News

RISC-V Zalasr Support Now Under Review For The Linux Kernel - Phoronix

Abstract Phoronix reports that support for the RISC-V Zalasr extension is currently under review for potential inclusion in the mainline Linux Kernel. This proposed extension aims to standardize and improve atomic load and

By Admin 5 Sep 2025 • 2 min read •

Research

Applications of AI in Space Domain (Full Report)

By Admin 3 Sep 2025 •

Research

Applications of AI in Space Domain

Abstract This comprehensive review examines the critical role of Artificial Intelligence in advancing autonomous space missions, spanning real-time data processing, celestial navigation, and on-board decision-making. The study highlights the significant architectural challenges associated

By Admin 3 Sep 2025 • 2 min read •

Research

Enhancing Large Language Models for Hardware Verification: A Novel SystemVerilog Assertion Dataset

Originally published on ACM Digital Library ACM Transactions on Design Automation of Electronic Systems, Volume 0, Issue ja, -Not available-.

By Admin 30 Aug 2025 •

Research

BePilot: An AI Programming Assistant for Compiler Backend Development (Full Report)

By Admin 28 Aug 2025 •

Research

BePilot: An AI Programming Assistant for Compiler Backend Development

Abstract BePilot is introduced as a specialized AI programming assistant designed to streamline the complex, architecture-specific development of compiler backends. The assistant targets the automation of tedious or error-prone tasks such as instruction

By Admin 28 Aug 2025 • 2 min read •

News

Condor Computing’s Cuzco, a High-Perf RISC-V Design at Hot Chip 2025 - ServeTheHome (Full Report)

By Admin 25 Aug 2025 •

News

Condor Computing’s Cuzco, a High-Perf RISC-V Design at Hot Chip 2025 - ServeTheHome

Abstract Condor Computing is set to unveil "Cuzco," a new high-performance processor design based on the open RISC-V instruction set architecture. This crucial development targets the demanding high-end computing sector, signaling

By Admin 25 Aug 2025 • 2 min read •