RISC-V

News

Tenstorrent Productizes RISC-V CPU And AI IP - EE Times

Abstract Tenstorrent, a company prominent in developing AI systems, is shifting its business strategy by officially productizing and licensing its core intellectual property (IP). This offering includes both their proprietary high-performance RISC-V CPU

By Admin 25 Sep 2025 • 2 min read •

News

Google, AWS, and NASA to Keynote RISC-V Summit North America 2025 - Embedded Computing Design (Full Report)

By Admin 24 Sep 2025 •

News

Google, AWS, and NASA to Keynote RISC-V Summit North America 2025 - Embedded Computing Design

Abstract The RISC-V Summit North America 2025 will prominently feature keynotes from major technology and government powerhouses, specifically Google, Amazon Web Services (AWS), and NASA. This high-profile participation validates RISC-V's transformation

By Admin 24 Sep 2025 • 2 min read •

News

RISC-V Acceleration for Deep Learning at the Edge - Electropages (Full Report)

By Admin 23 Sep 2025 •

Research

Chip Industry Technical Paper Roundup: Sept 23 - Semiconductor Engineering (Full Report)

By Admin 23 Sep 2025 •

News

RISC-V Acceleration for Deep Learning at the Edge - Electropages

Abstract The article discusses the growing utilization of the open RISC-V Instruction Set Architecture (ISA) coupled with specialized hardware accelerators to meet the demanding requirements of Deep Learning inference at the edge. By

By Admin 23 Sep 2025 • 2 min read •

Research

Chip Industry Technical Paper Roundup: Sept 23 - Semiconductor Engineering

Abstract The analysis of the 'Chip Industry Technical Paper Roundup: Sept 23' is incomplete because the actual text content of the summarized technical papers was not provided, only the title and

By Admin 23 Sep 2025 • 1 min read •

News

RISC-V: Shaping the Future of Mobility with Open Standards - EE Times (Full Report)

By Admin 16 Sep 2025 •

🔒 Members

Research

HW/SW Co-Design to Retarget the Compiler For RISC-V Custom Instructions (Tampere Univ.) - Semiconductor Engineering (Full Report)

By Admin 16 Sep 2025 •

Research

HW/SW Co-Design to Retarget the Compiler For RISC-V Custom Instructions (Tampere Univ.) - Semiconductor Engineering

Abstract The research by Tampere University introduces an HW/SW co-design methodology aimed at efficiently integrating custom instruction set extensions (ISEs) into RISC-V cores. This approach specifically focuses on solving the typically time-consuming

By Admin 16 Sep 2025 • 2 min read •

News

RISC-V: Shaping the Future of Mobility with Open Standards - EE Times

Abstract RISC-V is emerging as the essential open standard architecture driving the future of mobility, specifically targeting advanced automotive applications like ADAS and high-performance computing in vehicles. The modular and customizable nature of

By Admin 16 Sep 2025 • 2 min read •

News

Condor Technology To Fly “Cuzco” RISC-V CPU Into The Datacenter - The Next Platform (Full Report)

By Admin 15 Sep 2025 •