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RISC-V hits 25% market penetration thanks to Meta and Qualcomm - Adafruit
Abstract
The RISC-V open-source architecture has achieved a significant milestone, reaching 25% market penetration in relevant sectors. This substantial growth is primarily driven by massive adoption and investment from major industry players, specifically
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Andrew “bunnie” Huang designs a “mostly open” RISC-V board - Adafruit
Abstract
Andrew “bunnie” Huang has designed a new RISC-V development board characterized by its commitment to a “mostly open” hardware philosophy. This project leverages the royalty-free RISC-V architecture to create a transparent, developer-friendly
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The RISC-V Revolution: Qualcomm’s Acquisition of Ventana Micro Systems Signals the End of the ARM-x86 Duopoly - FinancialContent
Abstract
Qualcomm’s acquisition of Ventana Micro Systems marks a pivotal moment, validating the RISC-V architecture's readiness to compete in high-performance computing markets traditionally dominated by ARM and x86. Ventana specializes
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U.S. must guard NASA’s future as China eyes space dominance | Opinion - Florida Today
Abstract
This opinion piece highlights the escalating geopolitical rivalry between the United States (NASA) and China for supremacy in space exploration, warning that China is aggressively pursuing space dominance. The article argues that
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Allwinner V861 dual-core 64-bit RISC-V AI Camera SiP features 128MB DDR3L, 4K H.265/H.264 video encoder - CNX Software
Abstract
Allwinner has introduced the V861, a new dual-core 64-bit RISC-V System-in-Package (SiP) specifically designed for advanced AI camera applications. This chip integrates 128MB of DDR3L memory directly, significantly simplifying hardware design and
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WCH CH32H417 dual-core RISC-V MCU offers USB 3.0, 500MB/s UHSIF, and Fast Ethernet interfaces - CNX Software
Abstract
WCH has announced the CH32H417, a new dual-core RISC-V MCU designed for high-speed data handling in embedded systems. The key innovation is the integration of advanced connectivity features, including native USB 3.