Research
Chip Industry Week in Review - Semiconductor Engineering
Originally published on Google News - RISC-V Research
Chip Industry Week in Review Semiconductor Engineering
RISC-V
News
Upbeat Technology’s RISC-V MCU Takes Flight With Near-Threshold Computing - All About Circuits
Abstract
Upbeat Technology has unveiled a new RISC-V Microcontroller Unit (MCU) that integrates sophisticated Near-Threshold Computing (NTC) technology. This innovation allows the chip to operate at minimal voltage levels, achieving dramatically improved energy
Research
SIMD-CP: SIMD with Redundant Bits Compression and Mixed-Precision Packing for Quantized DNNs
Abstract
SIMD-CP is a novel architectural approach designed to significantly accelerate quantized Deep Neural Networks (DNNs) by enhancing Single Instruction, Multiple Data (SIMD) processing. It integrates redundant bits compression to reduce data transfer
News
Upbeat Technology and SiFive Introduce Next-Gen Ultra-Low Power RISC-V MCU with AI Acceleration - PR Newswire
Abstract
Upbeat Technology and SiFive have jointly announced a next-generation Ultra-Low Power RISC-V Microcontroller Unit (MCU) designed specifically for advanced edge computing. The key innovation is the integration of dedicated AI acceleration capabilities
News
RISC-V International to announce 25% market penetration - New Electronics
Abstract
RISC-V International is poised to announce a significant achievement: 25% market penetration for its open standard Instruction Set Architecture (ISA). This milestone signals the rapid transition of RISC-V from an academic curiosity
Research
Near-Optimal Cache Sharing through Co-Located Parallel Scheduling of Threads
Abstract
This work introduces a novel mechanism, Co-Located Parallel Scheduling, aimed at achieving near-optimal efficiency in shared cache utilization among competing threads. The innovation focuses on intelligently grouping and scheduling threads whose memory