RISC-V

Research

Chip Industry Technical Paper Roundup: Nov. 26 - Semiconductor Engineering

Abstract This article compiles and summarizes recent technical papers detailing critical advancements across the semiconductor industry, focusing on cutting-edge R&D efforts. Key areas explored typically include solutions for managing power and

By Admin 26 Nov 2025 • 2 min read •

RISC-V

Enabling High Performance RISC-V Software for AI in the Real World (Full Report)

By Admin 25 Nov 2025 • 1 min read •

RISC-V

Enabling High Performance RISC-V Software for AI in the Real World

Abstract Embecosm demonstrated the successful acceleration of PyTorch AI workloads on RISC-V cores using the oneAPI Construction Kit. This effort, presented at RISC-V Europe 2025, showcased the portability of the unified oneAPI ecosystem,

By Admin 25 Nov 2025 • 2 min read •

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News

Roadmap for Open-Source Chiplet-Based RISC-V Systems For HPC and AI (ETH Zurich, Univ. of Bologna) - Semiconductor Engineering (Full Report)

By Admin 25 Nov 2025 •

News

Roadmap for Open-Source Chiplet-Based RISC-V Systems For HPC and AI (ETH Zurich, Univ. of Bologna) - Semiconductor Engineering

Abstract Researchers from ETH Zurich and the University of Bologna have proposed a definitive roadmap for creating next-generation HPC and AI systems based entirely on open-source RISC-V processors and modular chiplet architectures. This

By Admin 25 Nov 2025 • 2 min read •

Research

The Innovation Engine: Government-Funded Academic Research (Full Report)

By Admin 25 Nov 2025 •

Research

It’s the Specification, Stupid! (Full Report)

By Admin 25 Nov 2025 •

Research

From University Research to Global Impact (Full Report)

By Admin 25 Nov 2025 •

Research

The Innovation Engine: Government-Funded Academic Research

Abstract This paper analyzes the crucial role of strategic government funding in incubating foundational technologies, specifically using the open-source development of the RISC-V Instruction Set Architecture (ISA) as a prime example. The research

By Admin 25 Nov 2025 • 2 min read •

Research

It’s the Specification, Stupid!

Abstract This article posits that the primary competitive advantage of the RISC-V architecture is its open, modular, and precise Instruction Set Architecture (ISA) specification, rather than any specific vendor implementation. The authors argue

By Admin 25 Nov 2025 • 2 min read •

Research

From University Research to Global Impact

Abstract The article traces the explosive growth and impact of the RISC-V Instruction Set Architecture (ISA), detailing its successful transition from academic research at UC Berkeley to a global, open-source hardware standard. It

By Admin 25 Nov 2025 • 2 min read •

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Research

Taurus: Towards A High-Performance and Generic Congestion Control Framework for Datacenter Networks (Full Report)

By Admin 25 Nov 2025 •