Research

Research

The BaseJump Manycore Accelerator Network

Abstract The BaseJump Manycore Accelerator Network is an open-source, mesh-based On-Chip-Network (OCN) developed using over 20 years of manycore architecture expertise. This scalable network served as the communication backbone for the 16nm 511-core

By Admin 2 Aug 2018 • 2 min read •

Research

A Scalable Near-Memory Architecture for Training Deep Neural Networks on Large In-Memory Datasets (Full Report)

By Admin 19 Feb 2018 • 3 min read •

Research

A Scalable Near-Memory Architecture for Training Deep Neural Networks on Large In-Memory Datasets

Abstract This paper proposes NTX, a scalable near-memory acceleration engine designed for high-precision training of deep neural networks, moving beyond the traditional focus on inference acceleration. NTX is implemented on the Logic Base

By Admin 19 Feb 2018 • 2 min read •

Research

Instruction-Level Abstraction (ILA): A Uniform Specification for System-on-Chip (SoC) Verification (Full Report)

By Admin 3 Jan 2018 • 3 min read •

Research

Instruction-Level Abstraction (ILA): A Uniform Specification for System-on-Chip (SoC) Verification

Abstract Modern Systems-on-Chip (SoC) designs require a new verification standard due to their heterogeneity and reliance on specialized accelerators, which traditional Instruction Set Architectures (ISA) fail to cover. This paper formalizes the Instruction-Level

By Admin 3 Jan 2018 • 2 min read •

Research

HERO: Heterogeneous Embedded Research Platform for Exploring RISC-V Manycore Accelerators on FPGA (Full Report)

By Admin 18 Dec 2017 • 3 min read •

Research

HERO: Heterogeneous Embedded Research Platform for Exploring RISC-V Manycore Accelerators on FPGA

Abstract HERO is an FPGA-based heterogeneous embedded research platform designed to combine an industry-standard host processor with an open, scalable programmable manycore accelerator (PMCA). The platform integrates a hard ARM Cortex-A multicore host

By Admin 18 Dec 2017 • 2 min read •

Research

The microarchitecture of a multi-threaded RISC-V compliant processing core family for IoT end-nodes (Full Report)

By Admin 13 Dec 2017 • 3 min read •

Research

The microarchitecture of a multi-threaded RISC-V compliant processing core family for IoT end-nodes

Abstract This paper presents the microarchitecture of an open-source, multi-threaded processing core family designed for low-power Internet-of-Things (IoT) end-nodes. The core is fully compliant with the RISC-V instruction set and maintains hardware compatibility

By Admin 13 Dec 2017 • 2 min read •

Research

Princeton finds bugs in RISC-V architecture ... - eeNews Europe (Full Report)

By Admin 19 Apr 2017 •

Research

Princeton finds bugs in RISC-V architecture ... - eeNews Europe

Abstract Researchers at Princeton University have identified significant architectural vulnerabilities or 'bugs' within the open-source RISC-V Instruction Set Architecture (ISA) specification. This discovery, covered by eeNews Europe, emphasizes the importance of

By Admin 19 Apr 2017 • 1 min read •

Research

System Bits: April 18 - Semiconductor Engineering (Full Report)

By Admin 18 Apr 2017 •