Research

Research

Formal Verification Of RISC-V Cores - Semiconductor Engineering

Abstract The article emphasizes the critical role of Formal Verification (FV) in the development lifecycle of RISC-V cores, ensuring functional correctness and adherence to the Instruction Set Architecture (ISA). It details how FV

By Admin 28 Feb 2019 • 2 min read •

Research

NTX: An Energy-efficient Streaming Accelerator for Floating-point Generalized Reduction Workloads in 22nm FD-SOI (Full Report)

By Admin 1 Dec 2018 • 3 min read •

Research

NTX: An Energy-efficient Streaming Accelerator for Floating-point Generalized Reduction Workloads in 22nm FD-SOI

Abstract NTX is an energy-efficient streaming accelerator designed for 32-bit floating-point generalized reduction workloads, including training large Deep Neural Networks. Implemented in 22nm FD-SOI technology and orchestrated by a RISC-V core, the accelerator

By Admin 1 Dec 2018 • 2 min read •

Research

JuxtaPiton: Enabling Heterogeneous-ISA Research with RISC-V and SPARC FPGA Soft-cores (Full Report)

By Admin 20 Nov 2018 • 3 min read •

Research

JuxtaPiton: Enabling Heterogeneous-ISA Research with RISC-V and SPARC FPGA Soft-cores

Abstract JuxtaPiton is introduced as the first open-source, general-purpose, heterogeneous-ISA processor designed to enable crucial energy efficiency research. It integrates a small RISC-V core alongside a modified OpenSPARC T1 core within the OpenPiton

By Admin 20 Nov 2018 • 1 min read •

Research

Formally Verifying WARP-V, an Open-Source TL-Verilog RISC-V Core Generator (Full Report)

By Admin 5 Nov 2018 • 3 min read •

Research

Formally Verifying WARP-V, an Open-Source TL-Verilog RISC-V Core Generator

Abstract This paper details the formal verification of WARP-V, an open-source RISC-V core generator developed using the timing-abstract, transaction-level TL-Verilog methodology. The verification employed the established riscv-formal framework, investigating the synergy between transaction-level

By Admin 5 Nov 2018 • 1 min read •

Research

RISC-V: More Than a Core - Semiconductor Engineering (Full Report)

By Admin 15 Oct 2018 •

Research

RISC-V: More Than a Core - Semiconductor Engineering

Abstract The article analyzes the maturation of the RISC-V ecosystem, arguing that its impact now extends far beyond the foundational Instruction Set Architecture (ISA). It emphasizes the critical role of surrounding elements, including

By Admin 15 Oct 2018 • 2 min read •

Research

CIDPro: Custom Instructions for Dynamic Program Diversification (Full Report)

By Admin 4 Sep 2018 • 3 min read •

Research

CIDPro: Custom Instructions for Dynamic Program Diversification

Abstract CIDPro is a novel framework that uses dynamic program diversification and custom instruction generation to mitigate timing side-channel attacks in embedded systems. It integrates the LLVM compiler and the RISC-V FPGA soft-processor,

By Admin 4 Sep 2018 • 2 min read •

Research

The BaseJump Manycore Accelerator Network (Full Report)

By Admin 2 Aug 2018 • 3 min read •