Research

Research

BRISC-V: An Open-Source Architecture Design Space Exploration Toolbox

Abstract BRISC-V is an open-source, parameterized, and synthesizable register-transfer level (RTL) platform designed for comprehensive architecture design space exploration of RISC-V systems. It provides highly modular components spanning simple single-core designs to complex

By Admin 27 Aug 2019 • 2 min read •

Research

Boosting the Bounds of Symbolic QED for Effective Pre-Silicon Verification of Processor Cores (Full Report)

By Admin 19 Aug 2019 • 3 min read •

Research

Boosting the Bounds of Symbolic QED for Effective Pre-Silicon Verification of Processor Cores

Abstract This work introduces a novel pre-silicon verification approach that systematically leverages Symbolic Quick Error Detection (SQED) combined with symbolic starting states to drastically improve the detection of deep logic bugs and Hardware

By Admin 19 Aug 2019 • 2 min read •

Research

PERI: A Posit Enabled RISC-V Core (Full Report)

By Admin 5 Aug 2019 • 3 min read •

Research

PERI: A Posit Enabled RISC-V Core

Abstract This paper introduces PERI, the first Posit Enabled RISC-V core, which integrates the advanced Posit arithmetic format—a superior alternative to IEEE 754—into the extensible RISC-V ISA. The implementation leverages the

By Admin 5 Aug 2019 • 2 min read •

Research

Ara: A 1 GHz+ Scalable and Energy-Efficient RISC-V Vector Processor with Multi-Precision Floating Point Support in 22 nm FD-SOI (Full Report)

By Admin 2 Jun 2019 • 3 min read •

Research

Ara: A 1 GHz+ Scalable and Energy-Efficient RISC-V Vector Processor with Multi-Precision Floating Point Support in 22 nm FD-SOI

Abstract Ara is a highly scalable and energy-efficient 64-bit vector processor based on the RISC-V vector extension (v0.5 draft), realized in 22 nm FD-SOI technology. Its lane-based microarchitecture achieves clock speeds exceeding

By Admin 2 Jun 2019 • 2 min read •

Research

Fast TLB Simulation for RISC-V Systems (Full Report)

By Admin 16 May 2019 • 3 min read •

Research

Fast TLB Simulation for RISC-V Systems

Abstract This paper introduces a novel, fast TLB simulation framework specifically designed for exploring Translation Lookaside Buffer (TLB) behaviors in multi-core RISC-V systems. Integrated into the QEMU dynamic binary translated emulator, the framework

By Admin 16 May 2019 • 2 min read •

Research

The Cost of Application-Class Processing: Energy and Performance Analysis of a Linux-ready 1.7GHz 64bit RISC-V Core in 22nm FDSOI Technology (Full Report)

By Admin 10 Apr 2019 • 3 min read •

Research

The Cost of Application-Class Processing: Energy and Performance Analysis of a Linux-ready 1.7GHz 64bit RISC-V Core in 22nm FDSOI Technology

Abstract This paper presents a thorough energy and performance analysis of Ariane, an open-source, single-issue 64-bit RISC-V core implemented for application-class processing and supporting the Linux OS. Taped-out in 22nm FDSOI technology, the

By Admin 10 Apr 2019 • 2 min read •

Research

Formal Verification Of RISC-V Cores - Semiconductor Engineering (Full Report)

By Admin 28 Feb 2019 •