Research
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SSR: A Stall Scheme Reducing Bubbles in Load-Use Hazard of RISC-V Pipeline
Abstract
This paper introduces SSR (Stall Scheme Reducing bubbles), a microarchitectural modification designed to reduce performance degradation caused by load-use hazards in RISC-V pipelines. The proposed method replaces the traditional ID-EXE stage stall
Research
Stream Semantic Registers: A Lightweight RISC-V ISA Extension Achieving Full Compute Utilization in Single-Issue Cores
Abstract
Stream Semantic Registers (SSR) is a lightweight, non-invasive RISC-V Instruction Set Architecture extension designed to overcome the von Neumann bottleneck in energy-efficient single-issue cores. SSR achieves full compute utilization by implicitly encoding
Research
Using Name Confusion to Enhance Security
Abstract
The paper introduces Name Confusion, a novel security concept implemented by the Phantom Name System (PNS), designed to thwart multiple classes of code-reuse attacks. PNS provides multiple randomized virtual addresses (N mappings)
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Sapphire: A Configurable Crypto-Processor for Post-Quantum Lattice-based Protocols
Abstract
Sapphire is a configurable crypto-processor designed to accelerate computationally intensive lattice-based post-quantum cryptography (PQC) protocols on low-power embedded devices. Utilizing optimizations such as a SHA-3-based PRNG and a single-port RAM NTT memory
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Researchers build first 16-bit, 14,000-transistor carbon nanotube chip - bit-tech.net
Abstract
Researchers have successfully engineered the world's first 16-bit microprocessor built entirely using carbon nanotube (CNT) technology. This groundbreaking chip integrates 14,000 transistors, marking a significant milestone in demonstrating the
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Researchers build first 16-bit, 14,000-transistor carbon nanotube chip - Bit-Tech
Originally published on Google News - RISC-V Research
Researchers build first 16-bit, 14,000-transistor carbon nanotube chip Bit-Tech