Research
Research
LiteX: an open-source SoC builder and library based on Migen Python DSL
Abstract
LiteX is an open-source, BSD-licensed SoC builder and IP library designed for creating full FPGA designs and Systems-on-Chip. Its originality lies in describing all IP components entirely using the Migen Python Internal
Research
Prevention of Microarchitectural Covert Channels on an Open-Source 64-bit RISC-V Core
Abstract
This paper addresses the prevention of microarchitectural covert channels that exploit shared hardware resources to leak information across OS security boundaries, focusing on the open-source 64-bit RISC-V Ariane core. Initial attempts using
Research
Energy-Efficient Hardware-Accelerated Synchronization for Shared-L1-Memory Multiprocessor Clusters
Abstract
This paper proposes a light-weight Hardware-Accelerated Synchronization and Communication Unit (SCU) designed for shared-L1-memory multiprocessor clusters operating under energy-efficient near-threshold computing (NTC) conditions. Integrated into an eight-core RISC-V cluster, the SCU significantly
Research
Cycle-Accurate Evaluation of Software-Hardware Co-Design of Decimal Computation in RISC-V Ecosystem
Abstract
This paper presents a cycle-accurate evaluation framework for software-hardware co-design solutions targeting decimal computation within the RISC-V ecosystem. The methodology involves integrating dedicated hardware, realized as an accelerator supporting new decimal-oriented instructions,
Research
A portable and Linux capable RISC-V computer system in Verilog HDL
Abstract
This paper introduces a novel, portable RISC-V computer system implemented entirely in Verilog HDL, explicitly designed to boot the Linux operating system. Addressing the scarcity of public, Linux-capable RISC-V systems, the proposed
Research
RVCoreP : An optimized RISC-V soft processor of five-stage pipelining
Abstract
RVCoreP is an optimized five-stage pipelined soft processor designed for FPGAs, implementing the RISC-V 32-bit Integer (RV32I) instruction set architecture. The processor incorporates three key optimization techniques focusing on instruction fetch/branch