Research
Research
The nanoPU: Redesigning the CPU-Network Interface to Minimize RPC Tail Latency
Abstract
The nanoPU is a new CPU architecture optimized for networking tasks, specifically designed to minimize tail latency for Remote Procedure Calls (RPCs). It achieves an extremely fast 65ns wire-to-wire latency—a 13x
Research
Composite Enclaves: Towards Disaggregated Trusted Execution
Abstract
Trusted Execution Environments (TEEs) traditionally fail to protect code leveraging specialized or disaggregated heterogeneous hardware outside the main CPU, due to their fixed hardware Trusted Computing Base (TCB). This paper proposes "
Research
A RISC-V SystemC-TLM simulator
Abstract
This work presents a SystemC-TLM based simulator for a RISC-V microcontroller, prioritizing simplicity and expandability for System-on-Chip (SoC) development. It integrates a full RISC-V Instruction Set Simulator (ISS) supporting key ISA extensions,
Research
Elasticlave: An Efficient Memory Model for Enclaves
Abstract
Elasticlave proposes a novel memory model for Trusted Execution Environments (TEEs) that overcomes the severe performance penalties associated with traditional spatial isolation models like Intel SGX. This innovation allows enclaves to selectively
Research
A Mixed-Precision RISC-V Processor for Extreme-Edge DNN Inference
Abstract
This work introduces the MPIC (Mixed Precision Inference Core), a novel RISC-V processor designed to efficiently execute fine-grained mixed-precision Quantized Neural Networks (QNNs) on extreme-edge microcontrollers. It solves the challenge of supporting
Research
An Embedded RISC-V Core with Fast Modular Multiplication
Abstract
This work introduces an embedded RISC-V core designed to address the security and power consumption challenges inherent in battery-operated IoT devices by accelerating cryptographic operations. The key innovation is an extended custom