Research
Research
XpulpNN: Enabling Energy Efficient and Flexible Inference of Quantized Neural Network on RISC-V based IoT End Nodes
Abstract
XpulpNN introduces lightweight RISC-V ISA extensions supporting 4-bit and 2-bit SIMD instructions to accelerate heavily Quantized Neural Network (QNN) inference on IoT end nodes. The architecture utilizes a parallel cluster of 8
Research
RVCoreP-32IC: A high-performance RISC-V soft processor with an efficient fetch unit supporting the compressed instructions
Abstract
This paper proposes RVCoreP-32IC, a high-performance RISC-V soft processor targeting FPGAs, featuring a novel instruction fetch unit engineered to efficiently support compressed instructions (RVC). Although RVC reduces code size by about 25%
Research
SIMF: Single-Instruction Multiple-Flush Mechanism for Processor Temporal Isolation
Abstract
Microarchitectural timing attacks exploit shared on-core state components like caches and TLBs, which are traditionally mitigated inefficiently using software-based flushing instructions. This paper introduces SIMF (Single-Instruction Multiple-Flush), a specialized hardware mechanism implemented
Research
AXES: Approximation Manager for Emerging Memory Architectures
Abstract
AXES is the first self-optimizing runtime manager designed to coordinate configurable approximation knobs across all levels of the memory hierarchy, overcoming the limitations of rigid, design-time policies. It continuously learns and updates
Research
Indirection Stream Semantic Register Architecture for Efficient Sparse-Dense Linear Algebra
Abstract
This work introduces the Indirection Stream Semantic Register Architecture, an enhancement to a memory-streaming RISC-V ISA extension designed to efficiently handle sparse-dense linear algebra, which traditionally suffers from indirect memory lookup bottlenecks.
Research
RVCoreP-32IM: An effective architecture to implement mul/div instructions for five stage RISC-V soft processors
Abstract
The RVCoreP-32IM architecture is proposed as an effective extension to the five-stage RVCoreP soft processor to efficiently implement the RISC-V M-extension (multiplication/division instructions). Utilizing a simple fork-join method to expand execution