Research
Research
Extending the RISC-V ISA for exploring advanced reconfigurable SIMD instructions
Abstract
This paper presents a novel set of non-standard vector instruction types designed to extend the RISC-V ISA for exploring advanced, reconfigurable SIMD operations. The authors introduce a high-performance, open-source RV32 IM softcore
Research
Isadora: Automated Information Flow Property Generation for Hardware Designs
Abstract
Isadora is an automated methodology designed to generate information flow specifications for hardware designs, eliminating the need for manual security specifications or threat models. It operates by combining information flow tracking and
Research
HeapSafe: Securing Unprotected Heaps in RISC-V
Abstract
HeapSafe is a novel, lightweight hardware-assisted security scheme designed to mitigate critical memory corruption vulnerabilities, such as heap overflow and use-after-free, in bare-metal RISC-V systems. The approach utilizes a configurable coprocessor, decoupled
Research
MetaSys: A Practical Open-Source Metadata Management System to Implement and Evaluate Cross-Layer Optimizations
Abstract
MetaSys is the first open-source, FPGA-based infrastructure, prototyped within a RISC-V core, designed to enable the rapid implementation and evaluation of diverse cross-layer hardware-software optimizations. It introduces a lightweight, generalized metadata management
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Research
RISC-V Targets Data Centers - Semiconductor Engineering
Abstract
RISC-V is actively targeting the data center market, transitioning from embedded systems to challenge established server architectures by focusing on customization and efficiency for demanding workloads. The open instruction set architecture (ISA)
Research
CodeAPeel: An Integrated and Layered Learning Technology For Computer Architecture Courses
Abstract
CodeAPeel is a novel, multi-layered learning technology for computer architecture courses that simulates instruction processing across compiler, assembly, and machine layers. Unlike simulators modeling real processors (e.g., RISC-V), CodeAPeel utilizes a