Research
Research
Arrow: A RISC-V Vector Accelerator for Machine Learning Inference
Abstract
This paper introduces Arrow, a configurable hardware accelerator architecture implementing a subset of the RISC-V v0.9 vector ISA extension, specifically targeting edge machine learning inference. Benchmarked against fundamental vector and matrix
Research
A Survey on RISC-V Security: Hardware and Architecture
Abstract
This paper presents the first comprehensive survey of security solutions for the open RISC-V Instruction Set Architecture (ISA), addressing a critical research gap in the rapidly evolving IoT landscape. It analyzes representative
Research
Flare: Flexible In-Network Allreduce
Abstract
Flare is a flexible programmable switch designed to accelerate the computationally intensive allreduce communication operation in distributed systems by offloading aggregation to the network. Existing in-network solutions lack customization for specific data
Research
Effective Pre-Silicon Verification of Processor Cores by Breaking the Bounds of Symbolic Quick Error Detection
Abstract
This paper introduces a novel pre-silicon verification approach that extends Symbolic Quick Error Detection (SQED) by incorporating symbolic starting states, effectively breaking the bounds of conventional verification. This methodology allows Bounded Model
Research
Towards Accurate Performance Modeling of RISC-V Designs
Abstract
This paper investigates the critical challenge of achieving high performance modeling accuracy using microarchitecture-level simulators, which traditionally prioritize speed over fidelity compared to RTL simulation. The authors conduct a detailed study using
Research
Side-Channel Attacks on RISC-V Processors: Current Progress, Challenges, and Opportunities
Abstract
This paper presents a comprehensive study of security vulnerabilities in modern RISC-V microprocessors stemming from side-channel attacks (SCAs) and their corresponding mitigation techniques. The analysis focuses on both hardware-exploitable attacks, specifically using