Research
Research
Dustin: A 16-Cores Parallel Ultra-Low-Power Cluster with 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode
Abstract
Dustin is a 16-core parallel ultra-low-power RISC-V cluster designed for edge devices, focusing on energy-intensive Deep Neural Network (DNN) workloads. Its key innovation is the support for fully flexible 2- to 32-bit
Research
HEROv2: Full-Stack Open-Source Research Platform for Heterogeneous Computing
Abstract
HEROv2 is an FPGA-based, full-stack, open-source research platform designed to enable fast and accurate exploration of heterogeneous computing architectures, circumventing the compromises of traditional simulators. It integrates application-class 64-bit hosts (ARMv8 or
Research
A Heterogeneous In-Memory Computing Cluster For Flexible End-to-End Inference of Real-World Deep Neural Networks
Abstract
This paper presents a heterogeneous, tightly-coupled clustered architecture integrating 8 RISC-V cores, an analog In-Memory Computing (IMC) accelerator, and digital accelerators, designed for flexible end-to-end deep neural network (DNN) inference in TinyML
Research
A Parallel SystemC Virtual Platform for Neuromorphic Architectures
Abstract
Simulating complex neuromorphic architectures and benchmarking demanding Artificial Neural Network (ANN) applications requires significant computational resources during the early design phase. This paper presents a novel parallel SystemC-based Virtual Platform (VP) specifically
Research
IMCRYPTO: An In-Memory Computing Fabric for AES Encryption and Decryption
Abstract
IMCRYPTO is a novel In-Memory Computing (IMC) fabric designed to accelerate AES encryption and decryption using a unified hardware architecture. This approach combines the (Inv)SubBytes and (Inv)MixColumns steps, leveraging high
Research
PERCIVAL: Open-Source Posit RISC-V Core with Quire Capability
Abstract
PERCIVAL is the first open-source, application-level RISC-V core to natively implement the complete posit arithmetic instruction set, critically including the quire fused operations. This implementation integrates the Xposit RISC-V extension into LLVM,