Research

Research

Leverage the Average: Averaged Sampling in Pre-Silicon Side-Channel Leakage Assessment

Abstract This paper introduces Averaged Sampling, a novel technique to significantly reduce the power simulation cost associated with pre-silicon side-channel leakage assessment. By downsampling and averaging high-resolution power traces, the methodology drastically cuts

By Admin 8 Apr 2022 • 2 min read •

Research

Systematic Prevention of On-Core Timing Channels by Full Temporal Partitioning (Full Report)

By Admin 24 Feb 2022 • 3 min read •

Research

Systematic Prevention of On-Core Timing Channels by Full Temporal Partitioning

Abstract This work addresses microarchitectural timing channels by proposing a systematic hardware defense mechanism based on full temporal partitioning. Leveraging the RISC-V ISA, the authors introduce a new temporal fence instruction, fence.t,

By Admin 24 Feb 2022 • 2 min read •

Research

RISC-V AI Chips Will Be Everywhere - IEEE Spectrum (Full Report)

By Admin 24 Feb 2022 •

Research

RISC-V AI Chips Will Be Everywhere - IEEE Spectrum

Abstract RISC-V architecture is rapidly emerging as the foundation for next-generation AI accelerators, promising ubiquity across diverse computing domains. This proliferation is driven by RISC-V's intrinsic flexibility, allowing developers to implement

By Admin 24 Feb 2022 • 2 min read •

Research

CVA6's Data cache: Structure and Behavior (Full Report)

By Admin 8 Feb 2022 • 3 min read •

Research

CVA6's Data cache: Structure and Behavior

Abstract This paper addresses the critical lack of detailed documentation regarding the data cache microarchitecture within the widely used RISC-V CVA6 core, a necessary precursor for successful security research. Since microarchitectural attacks like

By Admin 8 Feb 2022 • 1 min read •

Research

CVA6's Data cache: Structure and Behavior

Originally published on ArXiv - Hardware Architecture Computer Science > Cryptography and Security arXiv:2202.03749v3 (cs) [Submitted on 8 Feb 2022 (v1), last revised 5 Jul 2022 (this version, v3)] Title:CVA6&

By Admin 8 Feb 2022 • 5 min read •

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Research

Do You Know For Sure Your RISC-V RTL Doesn’t Contain Any Surprises? - Semiconductor Engineering (Full Report)

By Admin 3 Feb 2022 •

Research

Do You Know For Sure Your RISC-V RTL Doesn’t Contain Any Surprises? - Semiconductor Engineering

Abstract The article critically examines the challenges associated with rigorous verification and validation of RISC-V Register Transfer Level (RTL) designs. It highlights the potential for hidden bugs, security vulnerabilities, or unintended features—termed

By Admin 3 Feb 2022 • 2 min read •

Research

DuVisor: a User-level Hypervisor Through Delegated Virtualization (Full Report)

By Admin 24 Jan 2022 • 3 min read •

Research

DuVisor: a User-level Hypervisor Through Delegated Virtualization

Abstract DuVisor introduces the concept of "delegated virtualization" to fundamentally redesign hypervisor architecture, achieving a purely user-level hypervisor by separating the control plane from the data plane. This design allows DuVisor

By Admin 24 Jan 2022 • 2 min read •