Research

Research

On the Simulation of Hypervisor Instructions for Accurate Timing Simulation of Virtualized Systems

Abstract Traditional full-system simulators for virtualized environments often abstract hypercalls, causing inaccurate timing results. This paper introduces a novel simulation approach that explicitly executes hypervisor instructions alongside OS and application code. This methodology,

By Admin 1 Jun 2022 • 1 min read •

Research

On-Demand Redundancy Grouping: Selectable Soft-Error Tolerance for a Multicore Cluster (Full Report)

By Admin 25 May 2022 • 3 min read •

Research

On-Demand Redundancy Grouping: Selectable Soft-Error Tolerance for a Multicore Cluster

Abstract This paper introduces On-Demand Redundancy Grouping (ODRG), a novel architectural scheme that provides selectable soft-error tolerance for multicore clusters operating in critical or hostile environments. Implemented on a six-core open-source RISC-V cluster,

By Admin 25 May 2022 • 2 min read •

Research

Design and Implementation of a Secure RISC-V Microprocessor (Full Report)

By Admin 10 May 2022 • 3 min read •

Research

Design and Implementation of a Secure RISC-V Microprocessor

Abstract The authors detail the design of a secure, bit-serial RISC-V microprocessor that mitigates side-channel attacks using automated, ubiquitous Boolean masking, ensuring all data remains protected without resorting to manual software countermeasures. This

By Admin 10 May 2022 • 2 min read •

Research

Monte Cimone: Paving the Road for the First Generation of RISC-V High-Performance Computers (Full Report)

By Admin 7 May 2022 • 3 min read •

Research

Monte Cimone: Paving the Road for the First Generation of RISC-V High-Performance Computers

Abstract Monte Cimone is a fully-operational, multi-blade computer prototype designed as a hardware-software test-bed to explore the challenges of integrating RISC-V into High-Performance Computing (HPC) environments. Utilizing the 64-bit U740 multi-core SoC, the

By Admin 7 May 2022 • 2 min read •

Research

RedMulE: A Compact FP16 Matrix-Multiplication Accelerator for Adaptive Deep Learning on RISC-V-Based Ultra-Low-Power SoCs (Full Report)

By Admin 24 Apr 2022 • 3 min read •

Research

RedMulE: A Compact FP16 Matrix-Multiplication Accelerator for Adaptive Deep Learning on RISC-V-Based Ultra-Low-Power SoCs

Abstract RedMulE is a compact, parametric FP16 matrix-multiplication accelerator designed to enable online finetuning and adaptation of Deep Learning models on ultra-low-power RISC-V-based SoCs. Integrating tightly within a PULP cluster, this engine addresses

By Admin 24 Apr 2022 • 2 min read •

Research

Fast Selective Flushing to Mitigate Contention-based Cache Timing Attacks (Full Report)

By Admin 12 Apr 2022 • 3 min read •

Research

Fast Selective Flushing to Mitigate Contention-based Cache Timing Attacks

Abstract This paper introduces Fast Selective Flushing (FaSe), a novel hardware/software countermeasure designed to mitigate contention-based cache timing attacks efficiently. FaSe utilizes a RISC-V ISA extension (one flush instruction) and minimal cache

By Admin 12 Apr 2022 • 2 min read •

Research

Leverage the Average: Averaged Sampling in Pre-Silicon Side-Channel Leakage Assessment (Full Report)

By Admin 8 Apr 2022 • 3 min read •