Research

Research

TinyVers: A Tiny Versatile System-on-chip with State-Retentive eMRAM for ML Inference at the Extreme Edge

Abstract TinyVers is an ultra-low power, versatile System-on-Chip designed for Machine Learning inference at the Extreme Edge, integrating a RISC-V host processor and a dataflow reconfigurable ML accelerator. The SoC leverages state-retentive embedded

By Admin 9 Jan 2023 • 2 min read •

Research

How Secure Are RISC-V Chips? - Semiconductor Engineering (Full Report)

By Admin 5 Jan 2023 •

Research

How Secure Are RISC-V Chips? - Semiconductor Engineering

Abstract The security of RISC-V chips is highly dependent on implementation quality and specific architecture extensions rather than being monolithic, posing unique verification and trust challenges due to its open and customizable nature.

By Admin 5 Jan 2023 • 2 min read •

Research

BARVINN: Arbitrary Precision DNN Accelerator Controlled by a RISC-V CPU (Full Report)

By Admin 31 Dec 2022 • 3 min read •

Research

BARVINN: Arbitrary Precision DNN Accelerator Controlled by a RISC-V CPU

Abstract BARVINN is an open-source DNN accelerator that enables deep learning inference at arbitrary precision using dedicated, bit-level configurable Processing Elements (PEs). The system is efficiently managed by a dedicated RISC-V CPU controller,

By Admin 31 Dec 2022 • 2 min read •

Research

RISC-V decoupled Vector Processing Unit (VPU) For HPC - Semiconductor Engineering (Full Report)

By Admin 20 Dec 2022 •

Research

RISC-V decoupled Vector Processing Unit (VPU) For HPC - Semiconductor Engineering

Abstract The article details a new RISC-V decoupled Vector Processing Unit (VPU) specifically designed to meet the rigorous demands of High-Performance Computing (HPC) applications. This architectural separation enhances throughput and improves latency tolerance

By Admin 20 Dec 2022 • 2 min read •

Research

Generic Tagging for RISC-V Binaries (Full Report)

By Admin 11 Dec 2022 • 3 min read •

Research

Generic Tagging for RISC-V Binaries

Abstract The paper introduces COGENT, a generic instruction tag generator designed for RISC-V binaries to simplify the implementation of custom hardware security solutions without requiring specialized compilers. COGENT associates configurable tags (1 to

By Admin 11 Dec 2022 • 2 min read •

Research

TCN-CUTIE: A 1036 TOp/s/W, 2.72 uJ/Inference, 12.2 mW All-Digital Ternary Accelerator in 22 nm FDX Technology (Full Report)

By Admin 1 Dec 2022 • 3 min read •

Research

TCN-CUTIE: A 1036 TOp/s/W, 2.72 uJ/Inference, 12.2 mW All-Digital Ternary Accelerator in 22 nm FDX Technology

Abstract TCN-CUTIE is a novel, all-digital ternary neural network accelerator implemented in 22 nm FDX technology and integrated into a RISC-V SoC, designed specifically for stringent TinyML constraints. It achieves a record peak

By Admin 1 Dec 2022 • 2 min read •

Research

HULK-V: a Heterogeneous Ultra-low-power Linux capable RISC-V SoC (Full Report)

By Admin 27 Nov 2022 • 3 min read •