Research

Research

A Classical Architecture For Digital Quantum Computers

Abstract This paper presents a scalable classical control architecture for digital quantum computers, tackling major scaling bottlenecks by integrating a multi-core RISC-V CPU with in-house control electronics. The architecture features parallel quantum operation

By Admin 23 May 2023 • 2 min read •

Research

Marsellus: A Heterogeneous RISC-V AI-IoT End-Node SoC with 2-to-8b DNN Acceleration and 30%-Boost Adaptive Body Biasing (Full Report)

By Admin 15 May 2023 • 4 min read •

Research

Marsellus: A Heterogeneous RISC-V AI-IoT End-Node SoC with 2-to-8b DNN Acceleration and 30%-Boost Adaptive Body Biasing

Abstract Marsellus is a heterogeneous RISC-V System-on-a-Chip designed for low-power AI-IoT end-nodes fabricated in GlobalFoundries 22nm FDX. The SoC combines a cluster of 16 RISC-V DSP cores supporting specialized 2-to-4b arithmetic (XpulpNN) with

By Admin 15 May 2023 • 2 min read •

Research

Echoes: a 200 GOPS/W Frequency Domain SoC with FFT Processor and I2S DSP for Flexible Data Acquisition from Microphone Arrays (Full Report)

By Admin 12 May 2023 • 3 min read •

Research

Echoes: a 200 GOPS/W Frequency Domain SoC with FFT Processor and I2S DSP for Flexible Data Acquisition from Microphone Arrays

Abstract ECHOES is a novel System-On-a-Chip designed for ultra-low-power, high-performance frequency domain processing required in demanding IoT applications like audio and radar. It integrates a specialized RISC-V core with DSP extensions and a

By Admin 12 May 2023 • 2 min read •

Research

Big-PERCIVAL: Exploring the Native Use of 64-Bit Posit Arithmetic in Scientific Computing (Full Report)

By Admin 11 May 2023 • 3 min read •

Research

Big-PERCIVAL: Exploring the Native Use of 64-Bit Posit Arithmetic in Scientific Computing

Abstract This work, titled "Big-PERCIVAL," explores the native implementation and use of 64-bit posit arithmetic (posit64) and associated quire operations by extending the PERCIVAL RISC-V core and Xposit custom ISA. Results

By Admin 11 May 2023 • 2 min read •

Research

Sparse Stream Semantic Registers: A Lightweight ISA Extension Accelerating General Sparse Linear Algebra (Full Report)

By Admin 9 May 2023 • 3 min read •

Research

Sparse Stream Semantic Registers: A Lightweight ISA Extension Accelerating General Sparse Linear Algebra

Abstract This paper introduces Sparse Stream Semantic Registers (SSSR), a lightweight ISA extension for RISC-V designed to accelerate general sparse linear algebra by efficiently handling both one- and two-sided operand sparsity. SSSR accelerates

By Admin 9 May 2023 • 2 min read •

Research

Cheshire: A Lightweight, Linux-Capable RISC-V Host Platform for Domain-Specific Accelerator Plug-In (Full Report)

By Admin 8 May 2023 • 3 min read •

Research

Cheshire: A Lightweight, Linux-Capable RISC-V Host Platform for Domain-Specific Accelerator Plug-In

Abstract Cheshire is a lightweight, Linux-capable 64-bit RISC-V host platform designed to facilitate the seamless integration of domain-specific accelerators, targeting energy-constrained IoT and TinyML applications. Its core architectural features include a unique low-pin-count

By Admin 8 May 2023 • 2 min read •

Research

NEUROPULS: NEUROmorphic energy-efficient secure accelerators based on Phase change materials aUgmented siLicon photonicS (Full Report)

By Admin 4 May 2023 • 3 min read •