Research

Research

Short reasons for long vectors in HPC CPUs: a study based on RISC-V

Abstract This study analyzes the performance benefits of exceptionally long vector units in High-Performance Computing (HPC) CPUs using a customizable RISC-V core setup. Testing vector lengths up to 256 double-precision elements against non-dense

By Admin 13 Sep 2023 • 1 min read •

Research

SG2042 64-Core RISC-V CPU Versus Existing RISC-V HW And High Performance x86 CPUs - Semiconductor Engineering (Full Report)

By Admin 13 Sep 2023 •

Research

SG2042 64-Core RISC-V CPU Versus Existing RISC-V HW And High Performance x86 CPUs - Semiconductor Engineering

Abstract The technical analysis focuses on the SG2042, a monumental 64-core CPU built upon the RISC-V instruction set architecture, representing a critical push into high-performance computing (HPC) markets. The study rigorously compares the

By Admin 13 Sep 2023 • 2 min read •

Research

Compressed Real Numbers for AI: a case-study using a RISC-V CPU (Full Report)

By Admin 11 Sep 2023 • 3 min read •

Research

Compressed Real Numbers for AI: a case-study using a RISC-V CPU

Abstract This paper investigates optimizing Deep Neural Network (DNN) inference on CPUs by utilizing compressed number formats like bfloat and posit to reduce memory bandwidth demands. The core innovation is proposing a method

By Admin 11 Sep 2023 • 2 min read •

Research

Octopus: A Heterogeneous In-network Computing Accelerator Enabling Deep Learning for network (Full Report)

By Admin 22 Aug 2023 • 3 min read •

Research

Octopus: A Heterogeneous In-network Computing Accelerator Enabling Deep Learning for network

Abstract The Octopus accelerator addresses the challenge of deploying Deep Learning (DL) models directly onto programmable in-network computing devices, which typically lack the necessary processing power and generality. It employs a heterogeneous architecture

By Admin 22 Aug 2023 • 2 min read •

Research

Unlocking Hardware Security Assurance: The Potential of LLMs (Full Report)

By Admin 21 Aug 2023 • 3 min read •

Research

Unlocking Hardware Security Assurance: The Potential of LLMs

Abstract This paper introduces the Natural Language Processing-based Security Property Generator (NSPG), a novel automated method designed to enhance hardware security assurance in complex System-on-Chips (SoCs). NSPG utilizes HS-BERT, the first language model

By Admin 21 Aug 2023 • 2 min read •

Research

Towards a Formally Verified Security Monitor for VM-based Confidential Computing (Full Report)

By Admin 20 Aug 2023 • 3 min read •

Research

Towards a Formally Verified Security Monitor for VM-based Confidential Computing

Abstract This paper proposes a novel methodology for formally modeling and proving a security monitor for VM-based confidential computing, addressing the lack of verification in existing systems critical for high-assurance applications. It introduces

By Admin 20 Aug 2023 • 2 min read •

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Understanding Lasso and Jolt, from theory to code - a16z crypto (Full Report)

By Admin 10 Aug 2023 •