Research

Research

Supporting Custom Instructions with the LLVM Compiler for RISC-V Processor

Abstract This study analyzes the process of integrating custom hardware instructions into the LLVM compiler backend for RISC-V processors, driven by the need for high-performance hardware accelerators. The authors delineate the required compiler

By Admin 23 Oct 2023 • 1 min read •

Research

A RISC-V MCU with adaptive reverse body bias and ultra-low-power retention mode in 22 nm FD-SOI (Full Report)

By Admin 13 Oct 2023 • 3 min read •

Research

A RISC-V MCU with adaptive reverse body bias and ultra-low-power retention mode in 22 nm FD-SOI

Abstract This paper introduces a highly energy-efficient 32-bit RISC-V MCU fabricated in 22 nm FD-SOI technology, utilizing adaptive reverse body biasing (RBB) to achieve ultra-low leakage current across the full industrial temperature range.

By Admin 13 Oct 2023 • 2 min read •

Research

Trikarenos: A Fault-Tolerant RISC-V-based Microcontroller for CubeSats in 28nm (Full Report)

By Admin 3 Oct 2023 • 3 min read •

Research

Trikarenos: A Fault-Tolerant RISC-V-based Microcontroller for CubeSats in 28nm

Abstract Trikarenos is a fault-tolerant, 32-bit RISC-V microcontroller SoC fabricated in an advanced TSMC 28nm technology, specifically designed to mitigate radiation-induced Single Event Upsets (SEUs) in harsh space environments like CubeSats. Its key

By Admin 3 Oct 2023 • 2 min read •

Research

Spatz: Clustering Compact RISC-V-Based Vector Units to Maximize Computing Efficiency (Full Report)

By Admin 18 Sep 2023 • 3 min read •

Research

Spatz: Clustering Compact RISC-V-Based Vector Units to Maximize Computing Efficiency

Abstract Spatz is a novel, compact 64-bit floating-point RISC-V vector processor utilizing the Zve64d extension, designed to maximize computing efficiency in clustered architectures. The architecture achieves peak energy efficiency by employing a highly

By Admin 18 Sep 2023 • 2 min read •

Research

Using LLMs to Facilitate Formal Verification of RTL (Full Report)

By Admin 18 Sep 2023 • 3 min read •

Research

Using LLMs to Facilitate Formal Verification of RTL

Abstract To mitigate the burden of writing SystemVerilog Assertions (SVA) for Formal Property Verification (FPV), this study explores using LLMs like GPT-4 to automatically generate verification properties directly from RTL code. Researchers designed

By Admin 18 Sep 2023 • 2 min read •

Research

A Precision-Scalable RISC-V DNN Processor with On-Device Learning Capability at the Extreme Edge (Full Report)

By Admin 15 Sep 2023 • 3 min read •

Research

A Precision-Scalable RISC-V DNN Processor with On-Device Learning Capability at the Extreme Edge

Abstract This paper presents a precision-scalable RISC-V DNN processor designed for extreme edge devices, tackling the challenges of efficient inference and enabling on-device learning. The architecture supports diverse fixed-point inference precisions ranging from

By Admin 15 Sep 2023 • 2 min read •

Research

Short reasons for long vectors in HPC CPUs: a study based on RISC-V (Full Report)

By Admin 13 Sep 2023 • 3 min read •