Research

Research

Secure Instruction and Data-Level Information Flow Tracking Model for RISC-V

Abstract This study proposes a novel multi-level granularity Information Flow Tracking (IFT) model designed specifically for the RISC-V architecture to enhance runtime security and system integrity. The approach integrates hardware-based IFT with a

By Admin 17 Nov 2023 • 2 min read •

Research

AXI-REALM: A Lightweight and Modular Interconnect Extension for Traffic Regulation and Monitoring of Heterogeneous Real-Time SoCs (Full Report)

By Admin 16 Nov 2023 • 3 min read •

Research

AXI-REALM: A Lightweight and Modular Interconnect Extension for Traffic Regulation and Monitoring of Heterogeneous Real-Time SoCs

Abstract AXI-REALM is a lightweight, modular, and open-source extension to AXI4 interconnects designed to restore timing predictability and control access contention in heterogeneous real-time SoCs. Utilizing a credit-based mechanism, AXI-REALM distributes and regulates

By Admin 16 Nov 2023 • 2 min read •

Research

PELS: A Lightweight and Flexible Peripheral Event Linking System for Ultra-Low Power IoT Processors (Full Report)

By Admin 16 Nov 2023 • 3 min read •

Research

PELS: A Lightweight and Flexible Peripheral Event Linking System for Ultra-Low Power IoT Processors

Abstract PELS (Peripheral Event Linking System) is proposed as a lightweight, flexible solution to manage peripheral interactions in ultra-low-power IoT processors without requiring continuous mediation by the main CPU. This open-source, peripheral-agnostic architecture

By Admin 16 Nov 2023 • 2 min read •

Research

CV32RT: Enabling Fast Interrupt and Context Switching for RISC-V Microcontrollers (Full Report)

By Admin 14 Nov 2023 • 3 min read •

Research

CV32RT: Enabling Fast Interrupt and Context Switching for RISC-V Microcontrollers

Abstract This work introduces CV32RT, an enhanced, open-source 32-bit RISC-V core designed to overcome the latency shortcomings of standard RISC-V interrupt handling in embedded systems. CV32RT integrates the RISC-V CLIC specification and features

By Admin 14 Nov 2023 • 1 min read •

Research

Ara2: Exploring Single- and Multi-Core Vector Processing with an Efficient RVV 1.0 Compliant Open-Source Processor (Full Report)

By Admin 13 Nov 2023 • 3 min read •

Research

Ara2: Exploring Single- and Multi-Core Vector Processing with an Efficient RVV 1.0 Compliant Open-Source Processor

Abstract Ara2 is presented as the first fully open-source vector processor compliant with the RISC-V V 1.0 frozen ISA, demonstrating state-of-the-art energy efficiency and achieving 95% functional-unit utilization on intensive workloads. Fabricated

By Admin 13 Nov 2023 • 2 min read •

Research

IndexMAC: A Custom RISC-V Vector Instruction to Accelerate Structured-Sparse Matrix Multiplications (Full Report)

By Admin 13 Nov 2023 • 3 min read •

Research

IndexMAC: A Custom RISC-V Vector Instruction to Accelerate Structured-Sparse Matrix Multiplications

Abstract This work introduces IndexMAC, a custom vector index-multiply-accumulate instruction proposed for RISC-V processors, designed to accelerate structured-sparse matrix multiplications (SSMM) critical to modern Machine Learning (ML) applications. IndexMAC enables low-cost indirect reads

By Admin 13 Nov 2023 • 2 min read •

Research

Supporting Custom Instructions with the LLVM Compiler for RISC-V Processor (Full Report)

By Admin 23 Oct 2023 • 3 min read •