Research

Research

China researchers report 256 core, chiplet-based processor ... - eeNews Europe

Abstract Researchers in China have unveiled a powerful processor featuring 256 cores, utilizing a scalable chiplet-based design. This architecture demonstrates significant progress in high-density, multi-core system development and validates the use of modular

By Admin 8 Jan 2024 • 2 min read •

Research

A Heterogeneous RISC-V based SoC for Secure Nano-UAV Navigation (Full Report)

By Admin 7 Jan 2024 • 4 min read •

Research

A Heterogeneous RISC-V based SoC for Secure Nano-UAV Navigation

Abstract The Shaheen SoC is a 9mm² heterogeneous RISC-V based processor designed to enable secure and autonomous navigation for energy-constrained nano-UAVs, addressing the need for advanced ML capabilities and secure operating system co-existence.

By Admin 7 Jan 2024 • 2 min read •

Research

TitanCFI: Toward Enforcing Control-Flow Integrity in the Root-of-Trust (Full Report)

By Admin 4 Jan 2024 • 3 min read •

Research

TitanCFI: Toward Enforcing Control-Flow Integrity in the Root-of-Trust

Abstract TitanCFI is a novel architecture designed to enforce Control-Flow Integrity (CFI) within the Root-of-Trust (RoT) on modern RISC-V platforms, mitigating attacks that divert control flow. This approach modifies the protected core'

By Admin 4 Jan 2024 • 2 min read •

Research

3 trends for 2024: AI drives more edge intelligence, RISC-V, & chiplets - embedded.com (Full Report)

By Admin 2 Jan 2024 •

Research

3 trends for 2024: AI drives more edge intelligence, RISC-V, & chiplets - embedded.com

Abstract The embedded technology landscape for 2024 is being rapidly reshaped by the confluence of three major trends: the expansion of AI processing to the edge, the increasing ubiquity and maturity of the

By Admin 2 Jan 2024 • 2 min read •

Research

Algorithms for Improving the Automatically Synthesized Instruction Set of an Extensible Processor (Full Report)

By Admin 1 Jan 2024 • 3 min read •

Research

Algorithms for Improving the Automatically Synthesized Instruction Set of an Extensible Processor

Abstract This paper introduces novel algorithms designed to optimize the automatically synthesized instruction sets (ISAs) used in extensible processors and hardware accelerators like RISC-V. The methods include a Common Operations Clustering algorithm to

By Admin 1 Jan 2024 • 2 min read •

Research

RHS-TRNG: A Resilient High-Speed True Random Number Generator Based on STT-MTJ Device (Full Report)

By Admin 29 Dec 2023 • 3 min read •

Research

RHS-TRNG: A Resilient High-Speed True Random Number Generator Based on STT-MTJ Device

Abstract The RHS-TRNG is a novel True Random Number Generator utilizing the stochastic switching characteristics of Spin-Transfer Torque Magnetic Tunnel Junction (STT-MTJ) devices to deliver high-quality randomness. This design achieves exceptional speed, reaching

By Admin 29 Dec 2023 • 2 min read •

Research

Siracusa: A 16 nm Heterogenous RISC-V SoC for Extended Reality with At-MRAM Neural Engine (Full Report)

By Admin 22 Dec 2023 • 3 min read •