Research
Research
LRSCwait: Enabling Scalable and Efficient Synchronization in Manycore Systems through Polling-Free and Retry-Free Operation
Abstract
The LRSCwait paper introduces LRwait and SCwait, a novel synchronization pair designed to eliminate performance-degrading polling and retries common in traditional Load-Reserved/Store-Conditional (LRSC) operations on manycore systems. The proposed Colibri architecture
Research
X-HEEP: An Open-Source, Configurable and Extendible RISC-V Microcontroller for the Exploration of Ultra-Low-Power Edge Accelerators
Abstract
X-HEEP (eXtendible Heterogeneous Energy-Efficient Platform) is an open-source, configurable RISC-V microcontroller designed to natively support and accelerate the integration of custom ultra-low-power edge accelerators. The platform offers extensive customization options, including variable
Research
The Next Front in the U.S.-China Battle Over Chips (Published 2024) - The New York Times
Abstract
The geopolitical chip war between the U.S. and China has shifted its focus to foundational open-source chip architectures, specifically RISC-V. China is rapidly adopting RISC-V as a strategic pathway to achieve
Research
MX: Enhancing RISC-V's Vector ISA for Ultra-Low Overhead, Energy-Efficient Matrix Multiplication
Abstract
The paper proposes Matrix eXtension (MX), a lightweight enhancement to the open-source RISC-V Vector (RVV) ISA designed to significantly boost the energy efficiency of Dense Matrix Multiplication (MatMul). MX avoids expensive dedicated
Research
MX: Enhancing RISC-V's Vector ISA for Ultra-Low Overhead, Energy-Efficient Matrix Multiplication
Originally published on ArXiv - Hardware Architecture
Computer Science > Hardware Architecture
arXiv:2401.04012v1 (cs)
[Submitted on 8 Jan 2024]
Title:MX: Enhancing RISC-V's Vector ISA for Ultra-Low Overhead, Energy-Efficient
Research
Floating Point HUB Adder for RISC-V Sargantana Processor
Abstract
This paper introduces a tailored Floating Point HUB Adder specifically implemented within the Sargantana RISC-V processor. The HUB format is utilized as an emerging technique to improve hardware requirements and reduce processing