Research
Research
QED: Scalable Verification of Hardware Memory Consistency
Abstract
QED is a novel, scalable verification methodology designed to detect complex Memory Consistency Model (MCM) bugs in out-of-order (OOO) processors, surpassing the severe scaling limits of prior bounded verification techniques. It achieves
Research
Integrating SystemC-AMS Power Modeling with a RISC-V ISS for Virtual Prototyping of Battery-operated Embedded Devices
Abstract
This paper presents an open-source framework addressing the gap in RISC-V simulation tools by integrating functional instruction set simulation (ISS) with detailed extra-functional power modeling. The framework combines GVSoC for functional RISC-V
Research
Electron-Tunnelling-Noise Programmable Random Variate Accelerator for Monte Carlo Sampling
Abstract
This article introduces an electron-tunneling-noise programmable random variate accelerator designed to drastically improve the sampling stage of Monte Carlo simulations. Integrated with a FemtoRV RISC-V soft processor using the LiteX framework on
Research
Analytical Heterogeneous Die-to-Die 3D Placement with Macros
Abstract
This paper introduces an innovative analytical framework for 3D mixed-size placement in heterogeneous, face-to-face (F2F) bonded 3D ICs, effectively integrating large macros and standard cells. The method employs a dedicated density model,
Research
PUMA: Efficient and Low-Cost Memory Allocation and Alignment Support for Processing-Using-Memory Architectures
Abstract
Processing-Using-DRAM (PUD) architectures require strict data alignment, mandating that operands reside in the same DRAM subarray and are aligned to row boundaries, constraints standard OS allocators cannot meet. This paper proposes PUMA,
Research
SSRESF: Sensitivity-aware Single-particle Radiation Effects Simulation Framework in SoC Platforms based on SVM Algorithm
Abstract
This paper introduces SSRESF, a Sensitivity-aware Single-particle Radiation Effects Simulation Framework designed to overcome the limitations of traditional radiation testing in large-scale System-on-Chip (SoC) designs. SSRESF utilizes the Support Vector Machine (SVM)