Research
Research
Lyra: A Hardware-Accelerated RISC-V Verification Framework with Generative Model-Based Processor Fuzzing
Abstract
Lyra is a novel heterogeneous RISC-V verification framework that pairs hardware acceleration via an FPGA SoC with an ISA-aware generative model, LyraGen, for processor fuzzing. This methodology enables high-throughput differential checking and
Research
Reproducibility and Standardization in gem5 Resources v25.0
Abstract
This paper introduces significant improvements in gem5 and gem5 Resources v25.0 to address critical challenges in simulation reproducibility and standardization within computer architecture research. Key innovations include standardizing disk image creation
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A Survey of Machine Learning Approaches in Logic Synthesis
Abstract
This survey provides a comprehensive review of the rapidly evolving landscape concerning the integration of Machine Learning (ML) techniques into classical Logic Synthesis workflows. It systematically categorizes various ML applications—ranging from
Research
svc-hook: hooking system calls on ARM64 by binary rewriting
Abstract
The paper introduces "svc-hook," a novel framework designed for intercepting and hooking system calls specifically on the ARM64 architecture. This highly effective instrumentation is achieved through the use of aggressive
Research
Recipe: Hardware-Accelerated Replication Protocols
Originally published on ACM Digital Library
Middleware '25: Proceedings of the 26th International Middleware Conference, Page 1-15.
Research
IM-PIR: In-Memory Private Information Retrieval
Abstract
IM-PIR introduces a novel architectural approach for Private Information Retrieval (PIR) by integrating the computationally intensive cryptographic operations directly into the memory subsystem, effectively addressing the data movement bottleneck known as the