Research
Research
A 0.96pJ/SOP, 30.23K-neuron/mm^2 Heterogeneous Neuromorphic Chip With Fullerene-like Interconnection Topology for Edge-AI Computing
Abstract
This work introduces a heterogeneous neuromorphic system-on-chip (SoC) designed for highly efficient Edge-AI computing, achieving an impressive energy consumption of 0.96 pJ/SOP. The architecture integrates a tightly coupled RISC-V CPU
Research
Optimizing Foundation Model Inference on a Many-tiny-core Open-source RISC-V Platform
Abstract
This work presents the first end-to-end inference results of transformer Foundation Models on a general-purpose, open-source many-tiny-core RISC-V platform, leveraging specialized ISA extensions and distributed primitives. The optimized implementation achieves significant speedups
Research
xTern: Energy-Efficient Ternary Neural Network Inference on RISC-V-Based Edge Systems
Abstract
xTern is a lightweight RISC-V instruction set architecture extension designed to accelerate Ternary Neural Network (TNN) inference on general-purpose edge cores. This ISA extension, complemented by optimized kernels, achieves 67% higher throughput
Research
Full-stack evaluation of Machine Learning inference workloads for RISC-V systems
Abstract
This study conducts a full-stack performance evaluation of diverse machine learning inference workloads on RISC-V architectures using the open-source gem5 architectural simulator. Leveraging an MLIR-based compilation toolchain, the research maps complex deep
Research
Using Formal Verification to Evaluate Single Event Upsets in a RISC-V Core
Abstract
This study employs formal verification, specifically model checking, to exhaustively evaluate the hardware reliability of the RISC-V Ibex Core against Single Event Upsets (SEUs), overcoming the coverage limitations of simulation-based fault injection.
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Research
Competitive Open-Source EDA Tools - Semiconductor Engineering
Abstract
The semiconductor industry is experiencing a significant shift with the maturation of competitive open-source Electronic Design Automation (EDA) tools that rival commercial offerings. This development drastically lowers the financial barrier to entry