Research

Research

Spatzformer: An Efficient Reconfigurable Dual-Core RISC-V V Cluster for Mixed Scalar-Vector Workloads

Abstract Spatzformer is the first reconfigurable dual-core RISC-V V (RVV) cluster designed to overcome the efficiency limitations of multi-core vector processors when facing mixed scalar-vector workloads. It operates in two modes—split mode

By Admin 7 Jul 2024 • 2 min read •

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Research

DAC 61: EDA addressing growing system complexity - embedded.com (Full Report)

By Admin 3 Jul 2024 •

Research

DAC 61: EDA addressing growing system complexity - embedded.com

Abstract The 61st Design Automation Conference (DAC 61) centered on how Electronic Design Automation (EDA) tools are evolving to tackle the exponentially growing complexity of modern electronic systems. Innovations focused heavily on managing

By Admin 3 Jul 2024 • 2 min read •

Research

RISC-V R-Extension: Advancing Efficiency with Rented-Pipeline for Edge DNN Processing (Full Report)

By Admin 2 Jul 2024 • 3 min read •

Research

RISC-V R-Extension: Advancing Efficiency with Rented-Pipeline for Edge DNN Processing

Abstract This paper introduces the RISC-V R-extension, a novel architectural approach designed to enhance Deep Neural Network (DNN) processing efficiency on lightweight edge devices. The R-extension avoids the high power, cost, and area

By Admin 2 Jul 2024 • 2 min read •

Research

AI-PiM—Extending the RISC-V processor with Processing-in-Memory functional units for AI inference at the edge of IoT - Frontiers (Full Report)

By Admin 27 Jun 2024 •

Research

AI-PiM—Extending the RISC-V processor with Processing-in-Memory functional units for AI inference at the edge of IoT - Frontiers

Abstract The AI-PiM project introduces a novel extension to the RISC-V processor architecture by integrating specialized Processing-in-Memory (PiM) functional units. This architectural enhancement is specifically designed to accelerate Artificial Intelligence (AI) inference tasks

By Admin 27 Jun 2024 • 2 min read •

Research

NoX: a Compact Open-Source RISC-V Processor for Multi-Processor Systems-on-Chip (Full Report)

By Admin 25 Jun 2024 • 3 min read •

Research

NoX: a Compact Open-Source RISC-V Processor for Multi-Processor Systems-on-Chip

Abstract The NoX processor is a compact, open-source, 32-bit RISC-V core designed in System Verilog to serve as a plug-and-play solution for Multi-Processor Systems-on-Chip (MPSoCs) targeting edge computing and IoT applications. It utilizes

By Admin 25 Jun 2024 • 2 min read •

Research

Design, Implementation and Evaluation of the SVNAPOT Extension on a RISC-V Processor (Full Report)

By Admin 22 Jun 2024 • 3 min read •

Research

Design, Implementation and Evaluation of the SVNAPOT Extension on a RISC-V Processor

Abstract The paper details the design, implementation, and evaluation of the RISC-V SVNAPOT Extension, intended to reduce Memory Management Unit (MMU) overhead during heavy memory loads. This extension leverages larger 64KB Natural-Power-of-Two (NAPOT)

By Admin 22 Jun 2024 • 2 min read •

Research

Basilisk: An End-to-End Open-Source Linux-Capable RISC-V SoC in 130nm CMOS (Full Report)

By Admin 21 Jun 2024 • 3 min read •