Research

Research

Exploiting the Lock: Leveraging MiG-V's Logic Locking for Secret-Data Extraction

Originally published on ArXiv - Hardware Architecture Computer Science > Cryptography and Security arXiv:2408.04976v1 (cs) [Submitted on 9 Aug 2024] Title:Exploiting the Lock: Leveraging MiG-V's Logic Locking for

By Admin 9 Aug 2024 • 5 min read •

Research

Deeploy: Enabling Energy-Efficient Deployment of Small Language Models On Heterogeneous Microcontrollers (Full Report)

By Admin 8 Aug 2024 • 3 min read •

Research

Deeploy: Enabling Energy-Efficient Deployment of Small Language Models On Heterogeneous Microcontrollers

Abstract Deeploy is a novel Deep Neural Network (DNN) compiler enabling the energy-efficient, end-to-end deployment of Small Language Models (SLMs) directly onto heterogeneous microcontroller (MCU) class chips without relying on external high-bandwidth memory.

By Admin 8 Aug 2024 • 2 min read •

Research

AI then and now - Jon Peddie (Full Report)

By Admin 7 Aug 2024 •

🔒 Members

Research

AI then and now - Jon Peddie Research (Full Report)

By Admin 7 Aug 2024 •

Research

AI then and now - Jon Peddie Research

Abstract The Jon Peddie Research article, "AI then and now," provides a historical overview, contrasting the computational challenges and theoretical foundations of early Artificial Intelligence with modern implementations. It details how

By Admin 7 Aug 2024 • 2 min read •

Research

AI then and now - Jon Peddie

Abstract Jon Peddie's analysis traces the history of Artificial Intelligence, contrasting early symbolic AI efforts with the current paradigm shift driven by Deep Learning and massive computational power. The article highlights

By Admin 7 Aug 2024 • 2 min read •

Research

Toward Attention-based TinyML: A Heterogeneous Accelerated Architecture and Automated Deployment Flow (Full Report)

By Admin 5 Aug 2024 • 3 min read •

Research

Toward Attention-based TinyML: A Heterogeneous Accelerated Architecture and Automated Deployment Flow

Abstract This work addresses the difficulty of running modern Attention-based Transformer models in resource-constrained Tiny Machine Learning (tinyML) environments. The authors introduce a heterogeneous RISC-V architecture, featuring an octa-core cluster coupled with a

By Admin 5 Aug 2024 • 2 min read •

Research

Functional ISS-Driven Verification of Superscalar RISC-V Processors (Full Report)

By Admin 30 Jul 2024 • 3 min read •

Research

Functional ISS-Driven Verification of Superscalar RISC-V Processors

Abstract This paper introduces SupeRFIVe, a novel methodology designed for the time-efficient and comprehensive functional verification of complex superscalar processors. SupeRFIVe leverages an Instruction Set Simulator (ISS) as a golden reference, interfacing with

By Admin 30 Jul 2024 • 1 min read •

Research

Switchboard: An Open-Source Framework for Modular Simulation of Large Hardware Systems (Full Report)

By Admin 30 Jul 2024 • 3 min read •