Research

Research

RISC-V Needs Secure 'Wheels': the MCU Initiator-Side Perspective

Originally published on ArXiv - Hardware Architecture Computer Science > Cryptography and Security arXiv:2410.09839v1 (cs) [Submitted on 13 Oct 2024] Title:RISC-V Needs Secure 'Wheels': the MCU Initiator-Side Perspective

By Admin 13 Oct 2024 • 5 min read •

Research

RISC-V V Vector Extension (RVV) with reduced number of vector registers (Full Report)

By Admin 10 Oct 2024 • 3 min read •

Research

RISC-V V Vector Extension (RVV) with reduced number of vector registers

Abstract This work proposes reducing the area overhead of the RISC-V V Vector Extension (RVV) specifically for use in small processors. The innovation is centered on reducing the standard 32 vector registers to

By Admin 10 Oct 2024 • 1 min read •

Research

vCLIC: Towards Fast Interrupt Handling in Virtualized RISC-V Mixed-criticality Systems (Full Report)

By Admin 10 Oct 2024 • 3 min read •

Research

vCLIC: Towards Fast Interrupt Handling in Virtualized RISC-V Mixed-criticality Systems

Abstract The paper introduces vCLIC, a novel hardware virtualization extension for the RISC-V Core Local Interrupt Controller (CLIC), designed to enhance performance in virtualized mixed-criticality systems. Addressing the limitations of current non-deterministic MSI

By Admin 10 Oct 2024 • 2 min read •

Research

Evaluation of Run-Time Energy Efficiency using Controlled Approximation in a RISC-V Core (Full Report)

By Admin 9 Oct 2024 • 3 min read •

Research

Evaluation of Run-Time Energy Efficiency using Controlled Approximation in a RISC-V Core

Abstract This study investigates dynamic hardware approximation techniques integrated into a specialized RISC-V core to improve energy efficiency in energy-constrained embedded systems. The platform achieved an average energy efficiency of 13.3 pJ/

By Admin 9 Oct 2024 • 2 min read •

Research

Secure Software/Hardware Hybrid In-Field Testing for System-on-Chip (Full Report)

By Admin 7 Oct 2024 • 3 min read •

Research

Secure Software/Hardware Hybrid In-Field Testing for System-on-Chip

Abstract This paper introduces a novel, low-overhead software/hardware hybrid approach for secure in-field testing of Systems-on-Chip (SoCs), addressing the security risks and technical limitations of traditional BIST methods. The core innovation utilizes

By Admin 7 Oct 2024 • 2 min read •

Research

KeyVisor -- A Lightweight ISA Extension for Protected Key Handles with CPU-enforced Usage Policies (Full Report)

By Admin 2 Oct 2024 • 3 min read •

Research

KeyVisor -- A Lightweight ISA Extension for Protected Key Handles with CPU-enforced Usage Policies

Abstract KeyVisor is a novel, lightweight ISA extension that securely offloads cryptographic key handling directly to the CPU, preventing keys from leaking to memory via software exploits or side channels. It introduces dedicated

By Admin 2 Oct 2024 • 2 min read •

Research

Using a Performance Model to Implement a Superscalar CVA6 (Full Report)

By Admin 2 Oct 2024 • 2 min read •