Research
Research
LOFMPL: An Open-source Logic Optimization Framework with MFFC-based Hypergraph Partition and Reinforcement Learning for Large Circuits
Abstract
LOFMPL is an open-source framework designed for advanced logic optimization, specifically targeting the challenges presented by extremely large integrated circuits. It utilizes a scalable, two-pronged optimization approach, starting with Maximal Fanout-Free Cone
Research
Hardware-Level QoS Enforcement Features: Technologies, Use Cases, and Research Challenges
Abstract
This comprehensive survey analyzes the landscape of hardware-level Quality of Service (QoS) enforcement features, critical for mitigating resource interference in modern multi-core and heterogeneous computing systems. The paper systematically reviews existing technologies,
Research
Toward Comprehensive Design Space Exploration on Heterogeneous Multi-core Processors
Abstract
Designing optimal heterogeneous multi-core processors requires navigating an exponentially large Design Space Exploration (DSE) covering core mixes, interconnects, and scheduling policies. This paper introduces a novel, comprehensive DSE framework specifically tailored for
Research
TEMpesT: Testing Empirically for Memory Transistency
Abstract
TEMpesT is a novel empirical testing methodology designed to rigorously verify memory transistency behaviors in modern CPU implementations, specifically targeting the complexities of the RISC-V Weak Memory Ordering (RVWMO) model. The system
Research
Efficient Flexible Edge Inference for Mixed-Precision Quantized DNN using Customized RISC-V Core
Abstract
This paper presents a customized RISC-V core architecture specifically designed for highly efficient and flexible edge inference of mixed-precision quantized Deep Neural Networks (DNNs). The core utilizes specialized instruction set extensions and
Research
Pipeline Stage Resolved Timing Characterization of FPGA and ASIC Implementations of a RISC V Processor
Abstract
This paper presents a pipeline stage resolved timing characterization framework to systematically compare a 32-bit RISC-V processor implemented on a 20 nm FPGA and a 7 nm FinFET ASIC. The analysis demonstrates