Research

Research

VEXP: A Low-Cost RISC-V ISA Extension for Accelerated Softmax Computation in Transformers

Abstract The VEXP project introduces a low-cost RISC-V Instruction Set Architecture (ISA) extension specifically designed to accelerate the Softmax computation bottleneck found in modern Transformer models. This is achieved by integrating a custom

By Admin 15 Apr 2025 • 2 min read •

Research

Unlimited Vector Processing for Wireless Baseband Based on RISC-V Extension (Full Report)

By Admin 15 Apr 2025 • 3 min read •

Research

Unlimited Vector Processing for Wireless Baseband Based on RISC-V Extension

Abstract This paper introduces the Unlimited Vector Processing (UVP) instruction set extension for RISC-V, specifically targeting performance improvements in wireless baseband processing (WBP). UVP overcomes conventional vector architecture constraints by implementing a novel

By Admin 15 Apr 2025 • 2 min read •

Research

AraOS: Analyzing the Impact of Virtual Memory Management on Vector Unit Performance (Full Report)

By Admin 14 Apr 2025 • 3 min read •

Research

AraOS: Analyzing the Impact of Virtual Memory Management on Vector Unit Performance

Abstract This work introduces AraOS, an integrated environment enabling full operating system (Linux) support for the open-source Ara2 RISC-V vector processor by sharing the Memory Management Unit (MMU) of the CVA6 scalar core.

By Admin 14 Apr 2025 • 2 min read •

Research

Efficient Architecture for RISC-V Vector Memory Access (Full Report)

By Admin 11 Apr 2025 • 3 min read •

Research

Efficient Architecture for RISC-V Vector Memory Access

Abstract Vector processors frequently suffer from inefficient memory accesses, particularly for strided and segment patterns, often relying on high-overhead crossbars or large transposition buffers. This paper presents EARTH, a novel RISC-V vector memory

By Admin 11 Apr 2025 • 2 min read •

Research

Empowering Vector Architectures for ML: The CAMP Architecture for Matrix Multiplication (Full Report)

By Admin 10 Apr 2025 • 3 min read •

Research

Empowering Vector Architectures for ML: The CAMP Architecture for Matrix Multiplication

Abstract This study introduces the Cartesian Accumulative Matrix Pipeline (CAMP) architecture, a novel design leveraging a hybrid multiplier to significantly enhance matrix multiplication within Vector Architectures (VAs) and SIMD units, optimized for Quantized

By Admin 10 Apr 2025 • 2 min read •

Research

Quadrilatero: A RISC-V programmable matrix coprocessor for low-power edge applications (Full Report)

By Admin 10 Apr 2025 • 3 min read •

Research

Quadrilatero: A RISC-V programmable matrix coprocessor for low-power edge applications

Abstract Quadrilatero is an open-source RISC-V programmable matrix coprocessor designed to optimize AI workloads in low-power edge applications. It utilizes a systolic array architecture and a streamlined matrix ISA extension to overcome the

By Admin 10 Apr 2025 • 2 min read •

Research

Just TestIt! An SBST Approach To Automate System-Integration Testing (Full Report)

By Admin 10 Apr 2025 • 3 min read •