Research
Research
AES-RV: Hardware-Efficient RISC-V Accelerator with Low-Latency AES Instruction Extension for IoT Security
Abstract
The AES-RV paper presents a hardware-efficient RISC-V accelerator featuring custom, low-latency AES instruction extensions optimized for real-time cryptographic processing in IoT systems. The architecture integrates high-bandwidth buffers, a specialized AES unit, and
Research
Scalable 28nm IC implementation of coupled oscillator network featuring tunable topology and complexity
Abstract
This work introduces a scalable, 28nm integrated circuit implementation of a coupled oscillator network designed to efficiently simulate complex dynamical systems for applications like analog computing and transport network stability analysis. The
Research
Enabling Syscall Intercept for RISC-V
Abstract
This paper details the efforts involved in porting a widely used syscall interception library to the RISC-V Instruction Set Architecture. The work is crucial for maturing the RISC-V software stack, enabling complex
Research
An Integrated UVM-TLM Co-Simulation Framework for RISC-V Functional Verification and Performance Evaluation
Abstract
This paper introduces an integrated UVM-TLM co-simulation framework designed to efficiently verify complex RISC-V processors by simultaneously evaluating functional correctness and performance. The methodology employs a configurable Transaction-Level Model (vmodel) of a
Research
Basilisk: A 34 mm2 End-to-End Open-Source 64-bit Linux-Capable RISC-V SoC in 130nm BiCMOS
Abstract
The Basilisk project introduces the largest end-to-end open-source system-on-chip (SoC) to date, successfully integrating a 64-bit Linux-capable RISC-V core on a 34 mm² die. Implemented in 130 nm BiCMOS technology, this effort
Research
Embedded GPU: An Open-Source And Configurable RISC-V GPU Platform for TinyAI Devices (EPFL) - Semiconductor Engineering
Abstract
EPFL has introduced the Embedded GPU (eGPU), an open-source and highly configurable GPU platform based on the RISC-V instruction set architecture. This innovation is specifically designed to accelerate graphics and computation tasks