Research

Research

Acore-CIM: build accurate and reliable mixed-signal CIM cores with RISC-V controlled self-calibration

Abstract Acore-CIM introduces a self-calibrated mixed-signal Compute-In-Memory (CIM) System-on-Chip (SoC) designed to overcome the integration and reliability challenges of analog AI accelerators. The architecture pairs dense SRAM weight storage with linear resistors for

By Admin 18 Jun 2025 • 2 min read •

Research

Chip Industry Technical Paper Roundup: June 17 - Semiconductor Engineering (Full Report)

By Admin 17 Jun 2025 •

Research

Chip Industry Technical Paper Roundup: June 17 - Semiconductor Engineering

Abstract This analysis reviews the scope of the 'Chip Industry Technical Paper Roundup: June 17' by Semiconductor Engineering. Due to the absence of the actual article content, a detailed summary of

By Admin 17 Jun 2025 • 1 min read •

Research

FeNN: A RISC-V vector processor for Spiking Neural Network acceleration (Full Report)

By Admin 13 Jun 2025 • 3 min read •

Research

FeNN: A RISC-V vector processor for Spiking Neural Network acceleration

Abstract The FeNN processor is a novel RISC-V-based soft vector processor specifically tailored for simulating energy-efficient Spiking Neural Networks (SNNs) on FPGAs. Unlike mainstream accelerators, FeNN is optimized for the low arithmetic intensity

By Admin 13 Jun 2025 • 2 min read •

Research

FractalSync: Lightweight Scalable Global Synchronization of Massive Bulk Synchronous Parallel AI Accelerators (Full Report)

By Admin 13 Jun 2025 • 3 min read •

Research

FractalSync: Lightweight Scalable Global Synchronization of Massive Bulk Synchronous Parallel AI Accelerators

Abstract FractalSync is a novel hardware-accelerated synchronization mechanism designed to address the challenges of coordinating massive parallel processing elements in Bulk Synchronous Parallel (BSP) AI accelerators. Integrated into the RISC-V based MAGIA platform,

By Admin 13 Jun 2025 • 2 min read •

Research

Towards Zero-Stall Matrix Multiplication on Energy-Efficient RISC-V Clusters for Machine Learning Acceleration (Full Report)

By Admin 12 Jun 2025 • 3 min read •

Research

Towards Zero-Stall Matrix Multiplication on Energy-Efficient RISC-V Clusters for Machine Learning Acceleration

Abstract This paper presents microarchitectural optimizations for energy-efficient RISC-V clusters aimed at achieving near zero-stall matrix multiplication for machine learning workloads. Key innovations include "zero-overhead loop nests" and a novel "

By Admin 12 Jun 2025 • 2 min read •

Research

Towards Base-Station-On-Chip: Wireless Communication Kernels On A RISC-V Vector Processor (TU Dresden, CeTI) - Semiconductor Engineering (Full Report)

By Admin 10 Jun 2025 •

Research

Towards Base-Station-On-Chip: Wireless Communication Kernels On A RISC-V Vector Processor (TU Dresden, CeTI) - Semiconductor Engineering

Abstract Researchers from TU Dresden's Center for Tactile Internet (CeTI) are investigating the potential of the RISC-V Vector Processor to efficiently handle demanding wireless communication kernels. This research aims to prove

By Admin 10 Jun 2025 • 2 min read •

Research

FREESS: An Educational Simulator of a RISC-V-Inspired Superscalar Processor Based on Tomasulo's Algorithm (Full Report)

By Admin 9 Jun 2025 • 3 min read •