Research

Research

Tag-Based Memory Verification System for RISC-V (Inha Univ., Intel Labs et al.) - Semiconductor Engineering

Abstract Researchers from Inha University and Intel Labs have jointly developed a novel Tag-Based Memory Verification System optimized for the RISC-V architecture. This hardware-assisted security mechanism utilizes tags, or metadata, associated with memory

By Admin 22 Jul 2025 • 2 min read •

Research

Analysis of RISC-V CPU Fuzzers via Automatic Bug Injection (ETH Zurich) - Semiconductor Engineering (Full Report)

By Admin 15 Jul 2025 •

Research

Analysis of RISC-V CPU Fuzzers via Automatic Bug Injection (ETH Zurich) - Semiconductor Engineering

Abstract ETH Zurich researchers introduced a novel method, Automatic Bug Injection (ABI), to rigorously analyze the effectiveness and limitations of current RISC-V CPU fuzzers. This technique systematically inserts predefined flaws into RISC-V core

By Admin 15 Jul 2025 • 2 min read •

Research

XiangShan: An Open Source Project for High-Performance RISC-V Processors Meeting Industrial-Grade Standards (Full Report)

By Admin 9 Jul 2025 •

Research

XiangShan: An Open Source Project for High-Performance RISC-V Processors Meeting Industrial-Grade Standards

Abstract The XiangShan project introduces a major open-source initiative dedicated to building high-performance RISC-V processors. Crucially, the design targets industrial-grade standards, ensuring the necessary reliability and robustness for commercial viability. This effort signifies

By Admin 9 Jul 2025 • 2 min read •

Research

Accelerating GenAI Workloads by Enabling RISC-V Microkernel Support in IREE (Full Report)

By Admin 7 Jul 2025 • 3 min read •

Research

Accelerating GenAI Workloads by Enabling RISC-V Microkernel Support in IREE

Abstract This paper focuses on accelerating Generative AI workloads by successfully integrating optimized microkernel support for the RISC-V architecture within IREE, an MLIR-based machine learning compiler and runtime. The core technical approach involves

By Admin 7 Jul 2025 • 1 min read •

Research

MEDEA: A Design-Time Multi-Objective Manager for Energy-Efficient DNN Inference on Heterogeneous Ultra-Low Power Platforms (Full Report)

By Admin 23 Jun 2025 • 3 min read •

Research

MEDEA: A Design-Time Multi-Objective Manager for Energy-Efficient DNN Inference on Heterogeneous Ultra-Low Power Platforms

Abstract MEDEA is a novel design-time multi-objective manager focused on maximizing energy efficiency for Deep Neural Network (DNN) inference on Heterogeneous Ultra-Low Power (HULP) platforms. It integrates kernel-level Dynamic Voltage and Frequency Scaling

By Admin 23 Jun 2025 • 2 min read •

Research

HetGPU: The pursuit of making binary compatibility towards GPUs (Full Report)

By Admin 19 Jun 2025 • 3 min read •

Research

HetGPU: The pursuit of making binary compatibility towards GPUs

Abstract HetGPU is a novel system designed to overcome the challenge of binary incompatibility across heterogeneous GPU vendors, including NVIDIA, AMD, Intel, and Tenstorrent. The system employs a compiler to generate an architecture-agnostic

By Admin 19 Jun 2025 • 2 min read •

Research

Acore-CIM: build accurate and reliable mixed-signal CIM cores with RISC-V controlled self-calibration (Full Report)

By Admin 18 Jun 2025 • 3 min read •