Research
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Bare-Metal RISC-V + NVDLA SoC for Efficient Deep Learning Inference
Abstract
This paper introduces a novel System-on-Chip (SoC) architecture that tightly couples a 32-bit Codasip uRISC_V core with the open-source NVDLA for efficient deep learning inference on edge devices. The core innovation
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Neural Network Quantization for Microcontrollers: A Comprehensive Survey of Methods, Platforms, and Applications
Abstract
This comprehensive survey addresses the challenges of deploying Quantized Neural Networks (QNNs) on resource-constrained microcontrollers (MCUs) within the TinyML paradigm. It systematically reviews hardware-oriented quantization methods, focusing on the critical trade-offs between
Research
VTR 9: Open-Source CAD for Fabric and Beyond FPGA Architecture Exploration
Abstract
VTR 9 represents a significant advancement in the open-source Verilog-to-Routing CAD flow, focusing on enabling comprehensive exploration of next-generation reconfigurable architectures. This release introduces powerful modeling capabilities for complex heterogeneous fabrics, moving
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IzhiRISC-V -- a RISC-V-based Processor with Custom ISA Extension for Spiking Neuron Networks Processing with Izhikevich Neurons
Abstract
This paper presents IzhiRISC-V, a specialized RISC-V-compliant processor engineered to overcome the inherent inefficiency of running Spiking Neural Networks (SNNs) on general-purpose hardware. The core innovation is a custom Instruction Set Architecture
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ARISE: Automating RISC-V Instruction Set Extension
Abstract
RISC-V's flexibility for custom instruction set extension (ISE) is often hindered by significant manual effort. The tool ARISE automates the generation of optimized RISC-V instructions by analyzing common assembly patterns
Research
Nail: Not Another Fault-Injection Framework for Chisel-generated RTL
Abstract
Nail is a new open-source fault injection (FI) framework designed for Chisel-generated RTL that overcomes limitations imposed by coarse, instruction-level controllability in existing tools. It introduces state-based faults, enabling complex scenarios that