Research
Research
Decentor-V: Lightweight ML Training on Low-Power RISC-V Edge Devices
Abstract
This paper introduces Decentor-V, a framework that enables lightweight Machine Learning training directly on low-power RISC-V edge devices, overcoming the architectural limitation imposed by the absence of dedicated Floating-Point Units (FPUs). By
Research
FASE: FPGA-Assisted Syscall Emulation for Rapid End-to-End Processor Performance Validation
Abstract
FASE (FPGA-Assisted Syscall Emulation) is a novel framework enabling rapid, early-stage processor performance validation by running complex multi-thread benchmarks directly on FPGA-hosted designs, bypassing the need for full SoC integration or a
Research
Lifetime-Aware Design of Item-Level Intelligence
Abstract
We present FlexiFlow, a lifetime-aware design framework utilizing natively flexible electronics and area-optimized RISC-V cores for Item-Level Intelligence (ILI) embedded in disposable products. The framework addresses the 1000X operational lifetime variability in
Research
basic_RV32s: An Open-Source Microarchitectural Roadmap for RISC-V RV32I
Abstract
This paper introduces BASICRV32s, an open-source framework detailing a practical microarchitectural roadmap for the RISC-V RV32I Instruction Set Architecture. The design follows an evolutionary pathway, progressing from a basic single-cycle core to
Research
HEEPidermis: a versatile SoC for BioZ recording
Abstract
HEEPidermis is a versatile System-on-Chip (SoC) designed to overcome the limitations of bulky, fixed-purpose hardware currently used for biological impedance (BioZ) recording. This SoC integrates a complete measurement pipeline, including specialized analog-to-digital
Research
Applications of AI in Space Domain
Abstract
This comprehensive review examines the critical role of Artificial Intelligence in advancing autonomous space missions, spanning real-time data processing, celestial navigation, and on-board decision-making. The study highlights the significant architectural challenges associated