Research
Research
Chiplet-Based RISC-V SoC with Modular AI Acceleration
Abstract
This paper introduces a novel chiplet-based RISC-V System-on-Chip designed to overcome the low manufacturing yields and rigidity of monolithic edge AI devices by utilizing a 30mm x 30mm silicon interposer. The architecture
Research
Automatic Microarchitecture-Aware Custom Instruction Design for RISC-V Processors
Abstract
Designing Application-Specific Instruction Set Processors (ASIPs) requires the manual identification of performance-enhancing custom instructions, a process addressed by this work's new automation tool. The paper introduces CIDRE (Custom Instruction Designer
Research
MaRVIn: A Cross-Layer Mixed-Precision RISC-V Framework for DNN Inference, from ISA Extension to Hardware Acceleration
Abstract
MaRVIn is a cross-layer hardware-software co-design framework that introduces novel ISA extensions and micro-architectural enhancements to optimize mixed-precision Deep Neural Network (DNN) inference on RISC-V processors. It tackles the inefficiency of standard
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HW/SW Co-Design to Retarget the Compiler For RISC-V Custom Instructions (Tampere Univ.) - Semiconductor Engineering
Abstract
The research by Tampere University introduces an HW/SW co-design methodology aimed at efficiently integrating custom instruction set extensions (ISEs) into RISC-V cores. This approach specifically focuses on solving the typically time-consuming
Research
SuperUROP: An FPGA-Based Spatial Accelerator for Sparse Matrix Operations
Abstract
Solving sparse linear systems is critical in numerical methods but suffers from poor data reuse and complex dependencies on current hardware. This paper presents SuperUROP, an FPGA implementation of the Azul spatial
Research
TurboFuzz: FPGA Accelerated Hardware Fuzzing for Processor Agile Verification
Abstract
TurboFuzz is an end-to-end hardware-accelerated verification framework that leverages a single FPGA to integrate the entire Test Generation, Simulation, and Coverage Feedback loop for modern processors. This architecture eliminates high host-FPGA communication