Research

Research

Proving and Rewarding Client Diversity to Strengthen Resilience of Blockchain Networks

Abstract This paper addresses the critical systemic risk in blockchain networks arising from the dominance of single client implementations by proposing mechanisms to prove and reward client diversity. The research details novel methods

By Admin 27 Oct 2025 • 2 min read •

Research

DRsam: Detection of Fault-Based Microarchitectural Side-Channel Attacks in RISC-V Using Statistical Preprocessing and Association Rule Mining (Full Report)

By Admin 21 Oct 2025 • 3 min read •

Research

DRsam: Detection of Fault-Based Microarchitectural Side-Channel Attacks in RISC-V Using Statistical Preprocessing and Association Rule Mining

Abstract DRsam is a novel detection method addressing the vulnerability of RISC-V processors to fault-based microarchitectural side-channel attacks, a security area often neglected compared to x86 and ARM. This approach combines statistical preprocessing

By Admin 21 Oct 2025 • 1 min read •

Research

SmaRTLy: RTL Optimization with Logic Inferencing and Structural Rebuilding (Full Report)

By Admin 20 Oct 2025 • 3 min read •

Research

SmaRTLy: RTL Optimization with Logic Inferencing and Structural Rebuilding

Abstract SmaRTLy is a novel RTL optimization technique specifically designed to enhance multiplexer tree synthesis by utilizing advanced logic inferencing and structural rebuilding methods. This approach overcomes the limitations of traditional synthesis tools

By Admin 20 Oct 2025 • 2 min read •

Research

Architect in the Loop Agentic Hardware Design and Verification (Full Report)

By Admin 19 Oct 2025 • 3 min read •

Research

Architect in the Loop Agentic Hardware Design and Verification

Abstract This paper proposes an "Architect in the Loop" agentic framework that automates the systematic and hierarchical design and verification of complex digital hardware, particularly processors. The methodology utilizes a combination

By Admin 19 Oct 2025 • 2 min read •

Research

Chip Industry Week in Review - Semiconductor Engineering

Originally published on Google News - RISC-V Research Chip Industry Week in Review  Semiconductor Engineering

By Admin 17 Oct 2025 •

Research

SIMD-CP: SIMD with Redundant Bits Compression and Mixed-Precision Packing for Quantized DNNs (Full Report)

By Admin 15 Oct 2025 •

Research

SIMD-CP: SIMD with Redundant Bits Compression and Mixed-Precision Packing for Quantized DNNs

Abstract SIMD-CP is a novel architectural approach designed to significantly accelerate quantized Deep Neural Networks (DNNs) by enhancing Single Instruction, Multiple Data (SIMD) processing. It integrates redundant bits compression to reduce data transfer

By Admin 15 Oct 2025 • 2 min read •

Research

ShuffleV: A Microarchitectural Defense Strategy against Electromagnetic Side-Channel Attacks in Microprocessors (Full Report)

By Admin 15 Oct 2025 • 3 min read •

Research

ShuffleV: A Microarchitectural Defense Strategy against Electromagnetic Side-Channel Attacks in Microprocessors

Abstract ShuffleV is a novel microarchitectural defense strategy developed to counter Electromagnetic Side-Channel Attacks (EM SCAs) by adopting a Moving Target Defense (MTD) philosophy. It integrates hardware units into the open-source RISC-V core

By Admin 15 Oct 2025 • 2 min read •