Research

Research

Sayram: A Hardware-software Co-design to Accelerate Wireless Baseband Processing

Abstract Sayram is a novel hardware-software co-design specifically developed to accelerate the computationally intensive tasks within wireless baseband processing, crucial for high-speed 5G communications. By integrating highly specialized hardware accelerators with optimized software

By Admin 13 Nov 2025 • 2 min read •

Research

Optimized Hyperdimensional Edge AI Evaluation for Efficiency and Reliability under Real Radiation (Full Report)

By Admin 11 Nov 2025 •

Research

Optimized Hyperdimensional Edge AI Evaluation for Efficiency and Reliability under Real Radiation

Abstract This paper presents an optimized Hyperdimensional Computing (HDC) framework specifically designed for efficiency-critical Edge AI applications. The methodology focuses on achieving high computational efficiency while simultaneously maximizing reliability and fault tolerance in

By Admin 11 Nov 2025 • 2 min read •

Research

Decoupled Control Flow and Data Access in RISC-V GPGPUs (Full Report)

By Admin 10 Nov 2025 • 3 min read •

Research

Decoupled Control Flow and Data Access in RISC-V GPGPUs

Abstract This paper addresses the performance limitations of Vortex, an open-source RISC-V GPGPU, by tackling high micro-code overheads associated with control flow (CF) management and memory access. The core innovation introduces decoupled CF

By Admin 10 Nov 2025 • 2 min read •

Research

FPGA-Accelerated RISC-V ISA Extensions for Efficient Neural Network Inference on Edge Devices (Full Report)

By Admin 10 Nov 2025 • 3 min read •

Research

FPGA-Accelerated RISC-V ISA Extensions for Efficient Neural Network Inference on Edge Devices

Abstract This paper presents novel FPGA-accelerated RISC-V instruction set architecture (ISA) extensions designed for efficient neural network inference on resource-constrained edge devices. The customized RISC-V core, featuring four domain-specific ISA extensions and integrated

By Admin 10 Nov 2025 • 2 min read •

Research

Hardware-Aware Neural Network Compilation with Learned Optimization: A RISC-V Accelerator Approach (Full Report)

By Admin 10 Nov 2025 • 3 min read •

Research

Hardware-Aware Neural Network Compilation with Learned Optimization: A RISC-V Accelerator Approach

Abstract The XgenSilicon ML Compiler is an automated end-to-end framework that optimizes high-level machine learning models into highly efficient RISC-V assembly code for custom ASIC accelerators. This system unifies software and hardware cost

By Admin 10 Nov 2025 • 2 min read •

Research

Bespoke Co-processor for Energy-Efficient Health Monitoring on RISC-V-based Flexible Wearables (Full Report)

By Admin 8 Nov 2025 • 3 min read •

Research

Bespoke Co-processor for Energy-Efficient Health Monitoring on RISC-V-based Flexible Wearables

Abstract This work introduces a highly energy-efficient, mechanically flexible RISC-V system designed for on-body health monitoring, addressing the challenges posed by the power constraints and limited gate counts of flexible electronics. The core

By Admin 8 Nov 2025 • 2 min read •

Research

MultiVic: A Time-Predictable RISC-V Multi-Core Processor Optimized for Neural Network Inference (Full Report)

By Admin 7 Nov 2025 • 3 min read •