Paper
Research
basic_RV32s: An Open-Source Microarchitectural Roadmap for RISC-V RV32I
Abstract
This paper introduces BASICRV32s, an open-source framework detailing a practical microarchitectural roadmap for the RISC-V RV32I Instruction Set Architecture. The design follows an evolutionary pathway, progressing from a basic single-
Research
HEEPidermis: a versatile SoC for BioZ recording
Abstract
HEEPidermis is a versatile System-on-Chip (SoC) designed to overcome the limitations of bulky, fixed-purpose hardware currently used for biological impedance (BioZ) recording. This SoC integrates a complete measurement pipeline,
Research
Microarchitecture Design and Benchmarking of Custom SHA-3 Instruction for RISC-V
Abstract
This study designs and benchmarks a custom SHA-3 permutation instruction directly integrated into the RISC-V CPU microarchitecture to address the limitations of standalone cryptographic accelerators. Using cycle-accurate GEM5 simulations
Research
Support Vector Machines Classification on Bendable RISC-V
Abstract
This paper addresses the challenge of implementing power-hungry Machine Learning (ML) algorithms on ultra-low-cost, lightweight Flexible Electronics (FE). The authors propose an open-source framework and a custom, precision-
Research
Building an Open CGRA Ecosystem for Agile Innovation
Abstract
This paper presents a comprehensive, open-source ecosystem centered on Coarse-Grained Reconfigurable Architectures (CGRAs) to enable agile hardware-software co-design for AI and edge computing workloads. Key contributions include HyCUBE,
Research
X-HEEP: An Open-Source, Configurable and Extendible RISC-V Platform for TinyAI Applications
Abstract
X-HEEP is an open-source, configurable RISC-V platform specifically designed for ultra-low-power edge applications (TinyAI). Its key innovation is the eXtendible Accelerator InterFace (XAIF), which enables seamless, highly