Paper

Research

MaRVIn: A Cross-Layer Mixed-Precision RISC-V Framework for DNN Inference, from ISA Extension to Hardware Acceleration (Full Report)

By Admin 18 Sep 2025 • 3 min read •

Research

MaRVIn: A Cross-Layer Mixed-Precision RISC-V Framework for DNN Inference, from ISA Extension to Hardware Acceleration

Abstract MaRVIn is a cross-layer hardware-software co-design framework that introduces novel ISA extensions and micro-architectural enhancements to optimize mixed-precision Deep Neural Network (DNN) inference on RISC-V processors. It tackles the inefficiency of standard

By Admin 18 Sep 2025 • 2 min read •

Research

SuperUROP: An FPGA-Based Spatial Accelerator for Sparse Matrix Operations (Full Report)

By Admin 15 Sep 2025 • 3 min read •

Research

SuperUROP: An FPGA-Based Spatial Accelerator for Sparse Matrix Operations

Abstract Solving sparse linear systems is critical in numerical methods but suffers from poor data reuse and complex dependencies on current hardware. This paper presents SuperUROP, an FPGA implementation of the Azul spatial

By Admin 15 Sep 2025 • 2 min read •

Research

TurboFuzz: FPGA Accelerated Hardware Fuzzing for Processor Agile Verification (Full Report)

By Admin 12 Sep 2025 • 3 min read •

Research

TurboFuzz: FPGA Accelerated Hardware Fuzzing for Processor Agile Verification

Abstract TurboFuzz is an end-to-end hardware-accelerated verification framework that leverages a single FPGA to integrate the entire Test Generation, Simulation, and Coverage Feedback loop for modern processors. This architecture eliminates high host-FPGA communication

By Admin 12 Sep 2025 • 2 min read •

Research

Decentor-V: Lightweight ML Training on Low-Power RISC-V Edge Devices (Full Report)

By Admin 10 Sep 2025 • 3 min read •

Research

Decentor-V: Lightweight ML Training on Low-Power RISC-V Edge Devices

Abstract This paper introduces Decentor-V, a framework that enables lightweight Machine Learning training directly on low-power RISC-V edge devices, overcoming the architectural limitation imposed by the absence of dedicated Floating-Point Units (FPUs). By

By Admin 10 Sep 2025 • 2 min read •

Research

FASE: FPGA-Assisted Syscall Emulation for Rapid End-to-End Processor Performance Validation (Full Report)

By Admin 10 Sep 2025 • 3 min read •

Research

FASE: FPGA-Assisted Syscall Emulation for Rapid End-to-End Processor Performance Validation

Abstract FASE (FPGA-Assisted Syscall Emulation) is a novel framework enabling rapid, early-stage processor performance validation by running complex multi-thread benchmarks directly on FPGA-hosted designs, bypassing the need for full SoC integration or a

By Admin 10 Sep 2025 • 2 min read •

Research

Lifetime-Aware Design of Item-Level Intelligence (Full Report)

By Admin 9 Sep 2025 • 3 min read •

Research

Lifetime-Aware Design of Item-Level Intelligence

Abstract We present FlexiFlow, a lifetime-aware design framework utilizing natively flexible electronics and area-optimized RISC-V cores for Item-Level Intelligence (ILI) embedded in disposable products. The framework addresses the 1000X operational lifetime variability in

By Admin 9 Sep 2025 • 2 min read •