Paper

Research

Epiphany-V: A 1024 processor 64-bit RISC System-On-Chip

Abstract The Epiphany-V project details the design of a highly parallel System-On-Chip featuring 1024 64-bit RISC processors fabricated using 16nm FinFET technology. This massively multi-core architecture integrates 64MB of on-chip SRAM and utilizes

By Admin 6 Oct 2016 • 1 min read •

Research

A near-threshold RISC-V core with DSP extensions for scalable IoT Endpoint Devices (Full Report)

By Admin 30 Aug 2016 • 3 min read •

Research

A near-threshold RISC-V core with DSP extensions for scalable IoT Endpoint Devices

Abstract This paper presents the design of an open-source RISC-V processor core optimized for Near-Threshold (NT) operation within scalable multi-core clusters targeting energy-constrained IoT endpoint devices. The core integrates instruction extensions for Digital

By Admin 30 Aug 2016 • 2 min read •

Research

TriCheck: Memory Model Verification at the Trisection of Software, Hardware, and ISA (Full Report)

By Admin 26 Aug 2016 • 3 min read •

Research

TriCheck: Memory Model Verification at the Trisection of Software, Hardware, and ISA

Abstract Memory Consistency Models (MCMs) are typically verified in isolation across the hardware-software stack, leading to unverified interactions between compilers, ISA, and hardware implementations. TriCheck is a novel toolflow designed for full-stack MCM

By Admin 26 Aug 2016 • 2 min read •

Research

The Renewed Case for the Reduced Instruction Set Computer: Avoiding ISA Bloat with Macro-Op Fusion for RISC-V (Full Report)

By Admin 8 Jul 2016 • 4 min read •

Research

The Renewed Case for the Reduced Instruction Set Computer: Avoiding ISA Bloat with Macro-Op Fusion for RISC-V

Abstract This paper renews the argument for Reduced Instruction Set Computers (RISC), demonstrating that the open RISC-V ISA, particularly its compressed variant (RV64GC), can achieve performance and code density superior to complex proprietary

By Admin 8 Jul 2016 • 2 min read •

Research

A Soft Processor Overlay with Tightly-coupled FPGA Accelerator (Full Report)

By Admin 21 Jun 2016 • 3 min read •

Research

A Soft Processor Overlay with Tightly-coupled FPGA Accelerator

Abstract This paper presents an open-source soft processor designed for tight integration within an FPGA overlay framework to facilitate full application acceleration. Leveraging the RISC-V instruction set and a 4-stage pipeline, the design

By Admin 21 Jun 2016 • 2 min read •

Research

GRVI Phalanx: A Massively Parallel RISC-V FPGA Accelerator Accelerator (Full Report)

By Admin 3 Jun 2016 • 3 min read •

Research

GRVI Phalanx: A Massively Parallel RISC-V FPGA Accelerator Accelerator

Abstract GRVI Phalanx is a massively parallel framework combining the FPGA-efficient RISC-V RV32I soft processor (GRVI) with a high-density parallel processor and accelerator array (Phalanx). This architecture utilizes shared memory clusters interconnected by

By Admin 3 Jun 2016 • 2 min read •

Research

Using System Hyper Pipelining (SHP) to Improve the Performance of a Coarse-Grained Reconfigurable Architecture (CGRA) Mapped on an FPGA (Full Report)

By Admin 28 Aug 2015 • 3 min read •